asm/mach-rc32434/ddr.h

0001 /*
0002  *  Definitions for the DDR registers
0003  *
0004  *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
0005  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
0006  *
0007  *  This program is free software; you can redistribute  it and/or modify it
0008  *  under  the terms of  the GNU General  Public License as published by the
0009  *  Free Software Foundation;  either version 2 of the  License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0013  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the  GNU General Public License along
0024  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  *
0027  */
0028
0029 #ifndef _ASM_RC32434_DDR_H_
0030 #define _ASM_RC32434_DDR_H_
0031
0032 #include <asm/mach-rc32434/rb.h>
0033
0034 /* DDR register structure */
0035 struct ddr_ram {
0036     u32 ddrbase;
0037     u32 ddrmask;
0038     u32 res1;
0039     u32 res2;
0040     u32 ddrc;
0041     u32 ddrabase;
0042     u32 ddramask;
0043     u32 ddramap;
0044     u32 ddrcust;
0045     u32 ddrrdc;
0046     u32 ddrspare;
0047 };
0048
0049 #define DDR0_PHYS_ADDR      0x18018000
0050
0051 /* DDR banks masks */
0052 #define DDR_MASK        0xffff0000
0053 #define DDR0_BASE_MSK       DDR_MASK
0054 #define DDR1_BASE_MSK       DDR_MASK
0055
0056 /* DDR bank0 registers */
0057 #define RC32434_DDR0_ATA_BIT        5
0058 #define RC32434_DDR0_ATA_MSK        0x000000E0
0059 #define RC32434_DDR0_DBW_BIT        8
0060 #define RC32434_DDR0_DBW_MSK        0x00000100
0061 #define RC32434_DDR0_WR_BIT     9
0062 #define RC32434_DDR0_WR_MSK     0x00000600
0063 #define RC32434_DDR0_PS_BIT     11
0064 #define RC32434_DDR0_PS_MSK     0x00001800
0065 #define RC32434_DDR0_DTYPE_BIT      13
0066 #define RC32434_DDR0_DTYPE_MSK      0x0000e000
0067 #define RC32434_DDR0_RFC_BIT        16
0068 #define RC32434_DDR0_RFC_MSK        0x000f0000
0069 #define RC32434_DDR0_RP_BIT     20
0070 #define RC32434_DDR0_RP_MSK     0x00300000
0071 #define RC32434_DDR0_AP_BIT     22
0072 #define RC32434_DDR0_AP_MSK     0x00400000
0073 #define RC32434_DDR0_RCD_BIT        23
0074 #define RC32434_DDR0_RCD_MSK        0x01800000
0075 #define RC32434_DDR0_CL_BIT     25
0076 #define RC32434_DDR0_CL_MSK     0x06000000
0077 #define RC32434_DDR0_DBM_BIT        27
0078 #define RC32434_DDR0_DBM_MSK        0x08000000
0079 #define RC32434_DDR0_SDS_BIT        28
0080 #define RC32434_DDR0_SDS_MSK        0x10000000
0081 #define RC32434_DDR0_ATP_BIT        29
0082 #define RC32434_DDR0_ATP_MSK        0x60000000
0083 #define RC32434_DDR0_RE_BIT     31
0084 #define RC32434_DDR0_RE_MSK     0x80000000
0085
0086 /* DDR bank C registers */
0087 #define RC32434_DDRC_MSK(x)     BIT_TO_MASK(x)
0088 #define RC32434_DDRC_CES_BIT        0
0089 #define RC32434_DDRC_ACE_BIT        1
0090
0091 /* Custom DDR bank registers */
0092 #define RC32434_DCST_MSK(x)     BIT_TO_MASK(x)
0093 #define RC32434_DCST_CS_BIT     0
0094 #define RC32434_DCST_CS_MSK     0x00000003
0095 #define RC32434_DCST_WE_BIT     2
0096 #define RC32434_DCST_RAS_BIT        3
0097 #define RC32434_DCST_CAS_BIT        4
0098 #define RC32434_DSCT_CKE_BIT        5
0099 #define RC32434_DSCT_BA_BIT     6
0100 #define RC32434_DSCT_BA_MSK     0x000000c0
0101
0102 /* DDR QSC registers */
0103 #define RC32434_QSC_DM_BIT      0
0104 #define RC32434_QSC_DM_MSK      0x00000003
0105 #define RC32434_QSC_DQSBS_BIT       2
0106 #define RC32434_QSC_DQSBS_MSK       0x000000fc
0107 #define RC32434_QSC_DB_BIT      8
0108 #define RC32434_QSC_DB_MSK      0x00000100
0109 #define RC32434_QSC_DBSP_BIT        9
0110 #define RC32434_QSC_DBSP_MSK        0x01fffe00
0111 #define RC32434_QSC_BDP_BIT     25
0112 #define RC32434_QSC_BDP_MSK     0x7e000000
0113
0114 /* DDR LLC registers */
0115 #define RC32434_LLC_EAO_BIT     0
0116 #define RC32434_LLC_EAO_MSK     0x00000001
0117 #define RC32434_LLC_EO_BIT      1
0118 #define RC32434_LLC_EO_MSK      0x0000003e
0119 #define RC32434_LLC_FS_BIT      6
0120 #define RC32434_LLC_FS_MSK      0x000000c0
0121 #define RC32434_LLC_AS_BIT      8
0122 #define RC32434_LLC_AS_MSK      0x00000700
0123 #define RC32434_LLC_SP_BIT      11
0124 #define RC32434_LLC_SP_MSK      0x001ff800
0125
0126 /* DDR LLFC registers */
0127 #define RC32434_LLFC_MSK(x)     BIT_TO_MASK(x)
0128 #define RC32434_LLFC_MEN_BIT        0
0129 #define RC32434_LLFC_EAN_BIT        1
0130 #define RC32434_LLFC_FF_BIT     2
0131
0132 /* DDR DLLTA registers */
0133 #define RC32434_DLLTA_ADDR_BIT      2
0134 #define RC32434_DLLTA_ADDR_MSK      0xfffffffc
0135
0136 /* DDR DLLED registers */
0137 #define RC32434_DLLED_MSK(x)        BIT_TO_MASK(x)
0138 #define RC32434_DLLED_DBE_BIT       0
0139 #define RC32434_DLLED_DTE_BIT       1
0140
0141 #endif  /* _ASM_RC32434_DDR_H_ */