asm/mach-ralink/rt305x.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Parts of this file are based on Ralink's 2.6.21 BSP
0005  *
0006  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0009  */
0010
0011 #ifndef _RT305X_REGS_H_
0012 #define _RT305X_REGS_H_
0013
0014 extern enum ralink_soc_type ralink_soc;
0015
0016 static inline int soc_is_rt3050(void)
0017 {
0018     return ralink_soc == RT305X_SOC_RT3050;
0019 }
0020
0021 static inline int soc_is_rt3052(void)
0022 {
0023     return ralink_soc == RT305X_SOC_RT3052;
0024 }
0025
0026 static inline int soc_is_rt305x(void)
0027 {
0028     return soc_is_rt3050() || soc_is_rt3052();
0029 }
0030
0031 static inline int soc_is_rt3350(void)
0032 {
0033     return ralink_soc == RT305X_SOC_RT3350;
0034 }
0035
0036 static inline int soc_is_rt3352(void)
0037 {
0038     return ralink_soc == RT305X_SOC_RT3352;
0039 }
0040
0041 static inline int soc_is_rt5350(void)
0042 {
0043     return ralink_soc == RT305X_SOC_RT5350;
0044 }
0045
0046 #define RT305X_SYSC_BASE        0x10000000
0047
0048 #define SYSC_REG_CHIP_NAME0     0x00
0049 #define SYSC_REG_CHIP_NAME1     0x04
0050 #define SYSC_REG_CHIP_ID        0x0c
0051 #define SYSC_REG_SYSTEM_CONFIG      0x10
0052
0053 #define RT3052_CHIP_NAME0       0x30335452
0054 #define RT3052_CHIP_NAME1       0x20203235
0055
0056 #define RT3350_CHIP_NAME0       0x33335452
0057 #define RT3350_CHIP_NAME1       0x20203035
0058
0059 #define RT3352_CHIP_NAME0       0x33335452
0060 #define RT3352_CHIP_NAME1       0x20203235
0061
0062 #define RT5350_CHIP_NAME0       0x33355452
0063 #define RT5350_CHIP_NAME1       0x20203035
0064
0065 #define CHIP_ID_ID_MASK         0xff
0066 #define CHIP_ID_ID_SHIFT        8
0067 #define CHIP_ID_REV_MASK        0xff
0068
0069 #define RT305X_SYSCFG_CPUCLK_SHIFT      18
0070 #define RT305X_SYSCFG_CPUCLK_MASK       0x1
0071 #define RT305X_SYSCFG_CPUCLK_LOW        0x0
0072 #define RT305X_SYSCFG_CPUCLK_HIGH       0x1
0073
0074 #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT   2
0075 #define RT305X_SYSCFG_CPUCLK_MASK       0x1
0076 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT     0x1
0077
0078 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8
0079 #define RT3352_SYSCFG0_CPUCLK_MASK  0x1
0080 #define RT3352_SYSCFG0_CPUCLK_LOW   0x0
0081 #define RT3352_SYSCFG0_CPUCLK_HIGH  0x1
0082
0083 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8
0084 #define RT5350_SYSCFG0_CPUCLK_MASK  0x3
0085 #define RT5350_SYSCFG0_CPUCLK_360   0x0
0086 #define RT5350_SYSCFG0_CPUCLK_320   0x2
0087 #define RT5350_SYSCFG0_CPUCLK_300   0x3
0088
0089 #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
0090 #define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
0091 #define RT5350_SYSCFG0_DRAM_SIZE_2M     0
0092 #define RT5350_SYSCFG0_DRAM_SIZE_8M     1
0093 #define RT5350_SYSCFG0_DRAM_SIZE_16M    2
0094 #define RT5350_SYSCFG0_DRAM_SIZE_32M    3
0095 #define RT5350_SYSCFG0_DRAM_SIZE_64M    4
0096
0097 /* multi function gpio pins */
0098 #define RT305X_GPIO_I2C_SD      1
0099 #define RT305X_GPIO_I2C_SCLK        2
0100 #define RT305X_GPIO_SPI_EN      3
0101 #define RT305X_GPIO_SPI_CLK     4
0102 /* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
0103 #define RT305X_GPIO_7           7
0104 #define RT305X_GPIO_10          10
0105 #define RT305X_GPIO_14          14
0106 #define RT305X_GPIO_UART1_TXD       15
0107 #define RT305X_GPIO_UART1_RXD       16
0108 #define RT305X_GPIO_JTAG_TDO        17
0109 #define RT305X_GPIO_JTAG_TDI        18
0110 #define RT305X_GPIO_MDIO_MDC        22
0111 #define RT305X_GPIO_MDIO_MDIO       23
0112 #define RT305X_GPIO_SDRAM_MD16      24
0113 #define RT305X_GPIO_SDRAM_MD31      39
0114 #define RT305X_GPIO_GE0_TXD0        40
0115 #define RT305X_GPIO_GE0_RXCLK       51
0116
0117 #define RT3352_SYSC_REG_SYSCFG0     0x010
0118 #define RT3352_SYSC_REG_SYSCFG1         0x014
0119 #define RT3352_SYSC_REG_CLKCFG1         0x030
0120 #define RT3352_SYSC_REG_RSTCTRL         0x034
0121 #define RT3352_SYSC_REG_USB_PS          0x05c
0122
0123 #define RT3352_CLKCFG0_XTAL_SEL     BIT(20)
0124 #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
0125 #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
0126 #define RT3352_RSTCTRL_UHST     BIT(22)
0127 #define RT3352_RSTCTRL_UDEV     BIT(25)
0128 #define RT3352_SYSCFG1_USB0_HOST_MODE   BIT(10)
0129
0130 #define RT305X_SDRAM_BASE       0x00000000
0131 #define RT305X_MEM_SIZE_MIN     2
0132 #define RT305X_MEM_SIZE_MAX     64
0133 #define RT3352_MEM_SIZE_MIN     2
0134 #define RT3352_MEM_SIZE_MAX     256
0135
0136 #endif