asm/mach-ralink/rt288x.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Parts of this file are based on Ralink's 2.6.21 BSP
0005  *
0006  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0009  */
0010
0011 #ifndef _RT288X_REGS_H_
0012 #define _RT288X_REGS_H_
0013
0014 #define RT2880_SYSC_BASE        0x00300000
0015
0016 #define SYSC_REG_CHIP_NAME0     0x00
0017 #define SYSC_REG_CHIP_NAME1     0x04
0018 #define SYSC_REG_CHIP_ID        0x0c
0019 #define SYSC_REG_SYSTEM_CONFIG      0x10
0020 #define SYSC_REG_CLKCFG         0x30
0021
0022 #define RT2880_CHIP_NAME0       0x38325452
0023 #define RT2880_CHIP_NAME1       0x20203038
0024
0025 #define CHIP_ID_ID_MASK         0xff
0026 #define CHIP_ID_ID_SHIFT        8
0027 #define CHIP_ID_REV_MASK        0xff
0028
0029 #define SYSTEM_CONFIG_CPUCLK_SHIFT  20
0030 #define SYSTEM_CONFIG_CPUCLK_MASK   0x3
0031 #define SYSTEM_CONFIG_CPUCLK_250    0x0
0032 #define SYSTEM_CONFIG_CPUCLK_266    0x1
0033 #define SYSTEM_CONFIG_CPUCLK_280    0x2
0034 #define SYSTEM_CONFIG_CPUCLK_300    0x3
0035
0036 #define CLKCFG_SRAM_CS_N_WDT        BIT(9)
0037
0038 #define RT2880_SDRAM_BASE       0x08000000
0039 #define RT2880_MEM_SIZE_MIN     2
0040 #define RT2880_MEM_SIZE_MAX     128
0041
0042 #endif