asm/mach-ralink/ralink_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Ralink SoC register definitions
0004  *
0005  *  Copyright (C) 2013 John Crispin <john@phrozen.org>
0006  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
0007  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  */
0009
0010 #ifndef _RALINK_REGS_H_
0011 #define _RALINK_REGS_H_
0012
0013 #include <linux/io.h>
0014
0015 enum ralink_soc_type {
0016     RALINK_UNKNOWN = 0,
0017     RT2880_SOC,
0018     RT3883_SOC,
0019     RT305X_SOC_RT3050,
0020     RT305X_SOC_RT3052,
0021     RT305X_SOC_RT3350,
0022     RT305X_SOC_RT3352,
0023     RT305X_SOC_RT5350,
0024     MT762X_SOC_MT7620A,
0025     MT762X_SOC_MT7620N,
0026     MT762X_SOC_MT7621AT,
0027     MT762X_SOC_MT7628AN,
0028     MT762X_SOC_MT7688,
0029 };
0030 extern enum ralink_soc_type ralink_soc;
0031
0032 extern __iomem void *rt_sysc_membase;
0033 extern __iomem void *rt_memc_membase;
0034
0035 static inline void rt_sysc_w32(u32 val, unsigned reg)
0036 {
0037     __raw_writel(val, rt_sysc_membase + reg);
0038 }
0039
0040 static inline u32 rt_sysc_r32(unsigned reg)
0041 {
0042     return __raw_readl(rt_sysc_membase + reg);
0043 }
0044
0045 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
0046 {
0047     u32 val = rt_sysc_r32(reg) & ~clr;
0048
0049     __raw_writel(val | set, rt_sysc_membase + reg);
0050 }
0051
0052 static inline void rt_memc_w32(u32 val, unsigned reg)
0053 {
0054     __raw_writel(val, rt_memc_membase + reg);
0055 }
0056
0057 static inline u32 rt_memc_r32(unsigned reg)
0058 {
0059     return __raw_readl(rt_memc_membase + reg);
0060 }
0061
0062 #endif /* _RALINK_REGS_H_ */