asm/mach-ralink/mt7620.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Parts of this file are based on Ralink's 2.6.21 BSP
0005  *
0006  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0007  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0008  * Copyright (C) 2013 John Crispin <john@phrozen.org>
0009  */
0010
0011 #ifndef _MT7620_REGS_H_
0012 #define _MT7620_REGS_H_
0013
0014 #define MT7620_SYSC_BASE        0x10000000
0015
0016 #define SYSC_REG_CHIP_NAME0     0x00
0017 #define SYSC_REG_CHIP_NAME1     0x04
0018 #define SYSC_REG_EFUSE_CFG      0x08
0019 #define SYSC_REG_CHIP_REV       0x0c
0020 #define SYSC_REG_SYSTEM_CONFIG0     0x10
0021 #define SYSC_REG_SYSTEM_CONFIG1     0x14
0022 #define SYSC_REG_CLKCFG0        0x2c
0023 #define SYSC_REG_CPU_SYS_CLKCFG     0x3c
0024 #define SYSC_REG_CPLL_CONFIG0       0x54
0025 #define SYSC_REG_CPLL_CONFIG1       0x58
0026
0027 #define MT7620_CHIP_NAME0       0x3637544d
0028 #define MT7620_CHIP_NAME1       0x20203032
0029 #define MT7628_CHIP_NAME1       0x20203832
0030
0031 #define SYSCFG0_XTAL_FREQ_SEL       BIT(6)
0032
0033 #define CHIP_REV_PKG_MASK       0x1
0034 #define CHIP_REV_PKG_SHIFT      16
0035 #define CHIP_REV_VER_MASK       0xf
0036 #define CHIP_REV_VER_SHIFT      8
0037 #define CHIP_REV_ECO_MASK       0xf
0038
0039 #define CLKCFG0_PERI_CLK_SEL        BIT(4)
0040
0041 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT  16
0042 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK   0xf
0043 #define CPU_SYS_CLKCFG_OCP_RATIO_1  0   /* 1:1   (Reserved) */
0044 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5    1   /* 1:1.5 (Reserved) */
0045 #define CPU_SYS_CLKCFG_OCP_RATIO_2  2   /* 1:2   */
0046 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5    3       /* 1:2.5 (Reserved) */
0047 #define CPU_SYS_CLKCFG_OCP_RATIO_3  4   /* 1:3   */
0048 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5    5   /* 1:3.5 (Reserved) */
0049 #define CPU_SYS_CLKCFG_OCP_RATIO_4  6   /* 1:4   */
0050 #define CPU_SYS_CLKCFG_OCP_RATIO_5  7   /* 1:5   */
0051 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8   /* 1:10  */
0052 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT   8
0053 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK    0x1f
0054 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT  0
0055 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK   0x1f
0056
0057 #define CPLL_CFG0_SW_CFG        BIT(31)
0058 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT  16
0059 #define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
0060 #define CPLL_CFG0_LC_CURFCK     BIT(15)
0061 #define CPLL_CFG0_BYPASS_REF_CLK    BIT(14)
0062 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT   10
0063 #define CPLL_CFG0_PLL_DIV_RATIO_MASK    0x3
0064
0065 #define CPLL_CFG1_CPU_AUX1      BIT(25)
0066 #define CPLL_CFG1_CPU_AUX0      BIT(24)
0067
0068 #define SYSCFG0_DRAM_TYPE_MASK      0x3
0069 #define SYSCFG0_DRAM_TYPE_SHIFT     4
0070 #define SYSCFG0_DRAM_TYPE_SDRAM     0
0071 #define SYSCFG0_DRAM_TYPE_DDR1      1
0072 #define SYSCFG0_DRAM_TYPE_DDR2      2
0073 #define SYSCFG0_DRAM_TYPE_UNKNOWN   3
0074
0075 #define SYSCFG0_DRAM_TYPE_DDR2_MT7628   0
0076 #define SYSCFG0_DRAM_TYPE_DDR1_MT7628   1
0077
0078 #define MT7620_DRAM_BASE        0x0
0079 #define MT7620_SDRAM_SIZE_MIN       2
0080 #define MT7620_SDRAM_SIZE_MAX       64
0081 #define MT7620_DDR1_SIZE_MIN        32
0082 #define MT7620_DDR1_SIZE_MAX        128
0083 #define MT7620_DDR2_SIZE_MIN        32
0084 #define MT7620_DDR2_SIZE_MAX        256
0085
0086 extern enum ralink_soc_type ralink_soc;
0087
0088 static inline int is_mt76x8(void)
0089 {
0090     return ralink_soc == MT762X_SOC_MT7628AN ||
0091            ralink_soc == MT762X_SOC_MT7688;
0092 }
0093
0094 static inline int mt7620_get_eco(void)
0095 {
0096     return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
0097 }
0098
0099 #endif