asm/mach-malta/kernel-entry-init.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Chris Dearman (chris@mips.com)
0007  * Copyright (C) 2007 Mips Technologies, Inc.
0008  * Copyright (C) 2014 Imagination Technologies Ltd.
0009  */
0010 #ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
0011 #define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
0012
0013 #include <asm/regdef.h>
0014 #include <asm/mipsregs.h>
0015
0016     /*
0017      * Prepare segments for EVA boot:
0018      *
0019      * This is in case the processor boots in legacy configuration
0020      * (SI_EVAReset is de-asserted and CONFIG5.K == 0)
0021      *
0022      * ========================= Mappings =============================
0023      * Virtual memory           Physical memory           Mapping
0024      * 0x00000000 - 0x7fffffff  0x80000000 - 0xfffffffff   MUSUK (kuseg)
0025      *                          Flat 2GB physical memory
0026      *
0027      * 0x80000000 - 0x9fffffff  0x00000000 - 0x1ffffffff   MUSUK (kseg0)
0028      * 0xa0000000 - 0xbf000000  0x00000000 - 0x1ffffffff   MUSUK (kseg1)
0029      * 0xc0000000 - 0xdfffffff             -                 MK  (kseg2)
0030      * 0xe0000000 - 0xffffffff             -                 MK  (kseg3)
0031      *
0032      *
0033      * Lowmem is expanded to 2GB
0034      *
0035      * The following code uses the t0, t1, t2 and ra registers without
0036      * previously preserving them.
0037      *
0038      */
0039     .macro  platform_eva_init
0040
0041     .set    push
0042     .set    reorder
0043     /*
0044      * Get Config.K0 value and use it to program
0045      * the segmentation registers
0046      */
0047     mfc0    t1, CP0_CONFIG
0048     andi    t1, 0x7 /* CCA */
0049     move    t2, t1
0050     ins t2, t1, 16, 3
0051     /* SegCtl0 */
0052     li      t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |     \
0053         (0 << MIPS_SEGCFG_PA_SHIFT) |               \
0054         (1 << MIPS_SEGCFG_EU_SHIFT)) |              \
0055         (((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) |        \
0056         (0 << MIPS_SEGCFG_PA_SHIFT) |               \
0057         (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
0058     or  t0, t2
0059     mtc0    t0, CP0_SEGCTL0
0060
0061     /* SegCtl1 */
0062     li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |  \
0063         (0 << MIPS_SEGCFG_PA_SHIFT) |               \
0064         (2 << MIPS_SEGCFG_C_SHIFT) |                \
0065         (1 << MIPS_SEGCFG_EU_SHIFT)) |              \
0066         (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |     \
0067         (0 << MIPS_SEGCFG_PA_SHIFT) |               \
0068         (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
0069     ins t0, t1, 16, 3
0070     mtc0    t0, CP0_SEGCTL1
0071
0072     /* SegCtl2 */
0073     li  t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |  \
0074         (6 << MIPS_SEGCFG_PA_SHIFT) |               \
0075         (1 << MIPS_SEGCFG_EU_SHIFT)) |              \
0076         (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |     \
0077         (4 << MIPS_SEGCFG_PA_SHIFT) |               \
0078         (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
0079     or  t0, t2
0080     mtc0    t0, CP0_SEGCTL2
0081
0082     jal mips_ihb
0083     mfc0    t0, $16, 5
0084     li      t2, 0x40000000      /* K bit */
0085     or      t0, t0, t2
0086     mtc0    t0, $16, 5
0087     sync
0088     jal mips_ihb
0089
0090     .set    pop
0091     .endm
0092
0093     .macro  kernel_entry_setup
0094
0095 #ifdef CONFIG_EVA
0096     sync
0097     ehb
0098
0099     mfc0    t1, CP0_CONFIG
0100     bgez    t1, 9f
0101     mfc0    t0, CP0_CONFIG, 1
0102     bgez    t0, 9f
0103     mfc0    t0, CP0_CONFIG, 2
0104     bgez    t0, 9f
0105     mfc0    t0, CP0_CONFIG, 3
0106     sll     t0, t0, 6   /* SC bit */
0107     bgez    t0, 9f
0108
0109     platform_eva_init
0110     b       0f
0111 9:
0112     /* Assume we came from YAMON... */
0113     PTR_LA  v0, 0x9fc00534  /* YAMON print */
0114     lw  v0, (v0)
0115     move    a0, zero
0116     PTR_LA  a1, nonsc_processor
0117     jal v0
0118
0119     PTR_LA  v0, 0x9fc00520  /* YAMON exit */
0120     lw  v0, (v0)
0121     li  a0, 1
0122     jal v0
0123
0124 1:  b   1b
0125     nop
0126     __INITDATA
0127 nonsc_processor:
0128     .asciz  "EVA kernel requires a MIPS core with Segment Control implemented\n"
0129     __FINIT
0130 #endif /* CONFIG_EVA */
0131 0:
0132     .endm
0133
0134 /*
0135  * Do SMP slave processor setup necessary before we can safely execute C code.
0136  */
0137     .macro  smp_slave_setup
0138 #ifdef CONFIG_EVA
0139     sync
0140     ehb
0141     platform_eva_init
0142 #endif
0143     .endm
0144
0145 #endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */