asm/mach-loongson32/regs-mux.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
0004  *
0005  * Loongson 1 MUX Register Definitions.
0006  */
0007
0008 #ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
0009 #define __ASM_MACH_LOONGSON32_REGS_MUX_H
0010
0011 #define LS1X_MUX_REG(x) \
0012         ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
0013
0014 #define LS1X_MUX_CTRL0          LS1X_MUX_REG(0x0)
0015 #define LS1X_MUX_CTRL1          LS1X_MUX_REG(0x4)
0016
0017 #if defined(CONFIG_LOONGSON1_LS1B)
0018 /* MUX CTRL0 Register Bits */
0019 #define UART0_USE_PWM23         BIT(28)
0020 #define UART0_USE_PWM01         BIT(27)
0021 #define UART1_USE_LCD0_5_6_11       BIT(26)
0022 #define I2C2_USE_CAN1           BIT(25)
0023 #define I2C1_USE_CAN0           BIT(24)
0024 #define NAND3_USE_UART5         BIT(23)
0025 #define NAND3_USE_UART4         BIT(22)
0026 #define NAND3_USE_UART1_DAT     BIT(21)
0027 #define NAND3_USE_UART1_CTS     BIT(20)
0028 #define NAND3_USE_PWM23         BIT(19)
0029 #define NAND3_USE_PWM01         BIT(18)
0030 #define NAND2_USE_UART5         BIT(17)
0031 #define NAND2_USE_UART4         BIT(16)
0032 #define NAND2_USE_UART1_DAT     BIT(15)
0033 #define NAND2_USE_UART1_CTS     BIT(14)
0034 #define NAND2_USE_PWM23         BIT(13)
0035 #define NAND2_USE_PWM01         BIT(12)
0036 #define NAND1_USE_UART5         BIT(11)
0037 #define NAND1_USE_UART4         BIT(10)
0038 #define NAND1_USE_UART1_DAT     BIT(9)
0039 #define NAND1_USE_UART1_CTS     BIT(8)
0040 #define NAND1_USE_PWM23         BIT(7)
0041 #define NAND1_USE_PWM01         BIT(6)
0042 #define GMAC1_USE_UART1         BIT(4)
0043 #define GMAC1_USE_UART0         BIT(3)
0044 #define LCD_USE_UART0_DAT       BIT(2)
0045 #define LCD_USE_UART15          BIT(1)
0046 #define LCD_USE_UART0           BIT(0)
0047
0048 /* MUX CTRL1 Register Bits */
0049 #define USB_RESET           BIT(31)
0050 #define SPI1_CS_USE_PWM01       BIT(24)
0051 #define SPI1_USE_CAN            BIT(23)
0052 #define DISABLE_DDR_CONFSPACE       BIT(20)
0053 #define DDR32TO16EN         BIT(16)
0054 #define GMAC1_SHUT          BIT(13)
0055 #define GMAC0_SHUT          BIT(12)
0056 #define USB_SHUT            BIT(11)
0057 #define UART1_3_USE_CAN1        BIT(5)
0058 #define UART1_2_USE_CAN0        BIT(4)
0059 #define GMAC1_USE_TXCLK         BIT(3)
0060 #define GMAC0_USE_TXCLK         BIT(2)
0061 #define GMAC1_USE_PWM23         BIT(1)
0062 #define GMAC0_USE_PWM01         BIT(0)
0063
0064 #elif defined(CONFIG_LOONGSON1_LS1C)
0065
0066 /* SHUT_CTRL Register Bits */
0067 #define UART_SPLIT          GENMASK(31, 30)
0068 #define OUTPUT_CLK          GENMASK(29, 26)
0069 #define ADC_SHUT            BIT(25)
0070 #define SDIO_SHUT           BIT(24)
0071 #define DMA2_SHUT           BIT(23)
0072 #define DMA1_SHUT           BIT(22)
0073 #define DMA0_SHUT           BIT(21)
0074 #define SPI1_SHUT           BIT(20)
0075 #define SPI0_SHUT           BIT(19)
0076 #define I2C2_SHUT           BIT(18)
0077 #define I2C1_SHUT           BIT(17)
0078 #define I2C0_SHUT           BIT(16)
0079 #define AC97_SHUT           BIT(15)
0080 #define I2S_SHUT            BIT(14)
0081 #define UART3_SHUT          BIT(13)
0082 #define UART2_SHUT          BIT(12)
0083 #define UART1_SHUT          BIT(11)
0084 #define UART0_SHUT          BIT(10)
0085 #define CAN1_SHUT           BIT(9)
0086 #define CAN0_SHUT           BIT(8)
0087 #define ECC_SHUT            BIT(7)
0088 #define GMAC_SHUT           BIT(6)
0089 #define USBHOST_SHUT            BIT(5)
0090 #define USBOTG_SHUT         BIT(4)
0091 #define SDRAM_SHUT          BIT(3)
0092 #define SRAM_SHUT           BIT(2)
0093 #define CAM_SHUT            BIT(1)
0094 #define LCD_SHUT            BIT(0)
0095
0096 #define UART_SPLIT_SHIFT                        30
0097 #define OUTPUT_CLK_SHIFT                        26
0098
0099 /* MISC_CTRL Register Bits */
0100 #define USBHOST_RSTN            BIT(31)
0101 #define PHY_INTF_SELI           GENMASK(30, 28)
0102 #define AC97_EN             BIT(25)
0103 #define SDIO_DMA_EN         GENMASK(24, 23)
0104 #define ADC_DMA_EN          BIT(22)
0105 #define SDIO_USE_SPI1           BIT(17)
0106 #define SDIO_USE_SPI0           BIT(16)
0107 #define SRAM_CTRL           GENMASK(15, 0)
0108
0109 #define PHY_INTF_SELI_SHIFT                     28
0110 #define SDIO_DMA_EN_SHIFT                       23
0111 #define SRAM_CTRL_SHIFT             0
0112
0113 #define LS1X_CBUS_REG(n, x) \
0114         ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
0115
0116 #define LS1X_CBUS_FIRST(n)      LS1X_CBUS_REG(n, 0x00)
0117 #define LS1X_CBUS_SECOND(n)     LS1X_CBUS_REG(n, 0x10)
0118 #define LS1X_CBUS_THIRD(n)      LS1X_CBUS_REG(n, 0x20)
0119 #define LS1X_CBUS_FOURTHT(n)        LS1X_CBUS_REG(n, 0x30)
0120 #define LS1X_CBUS_FIFTHT(n)     LS1X_CBUS_REG(n, 0x40)
0121
0122 #endif
0123
0124 #endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */