asm/mach-loongson32/regs-clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
0004  *
0005  * Loongson 1 Clock Register Definitions.
0006  */
0007
0008 #ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
0009 #define __ASM_MACH_LOONGSON32_REGS_CLK_H
0010
0011 #define LS1X_CLK_REG(x) \
0012         ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
0013
0014 #define LS1X_CLK_PLL_FREQ       LS1X_CLK_REG(0x0)
0015 #define LS1X_CLK_PLL_DIV        LS1X_CLK_REG(0x4)
0016
0017 #if defined(CONFIG_LOONGSON1_LS1B)
0018 /* Clock PLL Divisor Register Bits */
0019 #define DIV_DC_EN           BIT(31)
0020 #define DIV_DC_RST          BIT(30)
0021 #define DIV_CPU_EN          BIT(25)
0022 #define DIV_CPU_RST         BIT(24)
0023 #define DIV_DDR_EN          BIT(19)
0024 #define DIV_DDR_RST         BIT(18)
0025 #define RST_DC_EN           BIT(5)
0026 #define RST_DC              BIT(4)
0027 #define RST_DDR_EN          BIT(3)
0028 #define RST_DDR             BIT(2)
0029 #define RST_CPU_EN          BIT(1)
0030 #define RST_CPU             BIT(0)
0031
0032 #define DIV_DC_SHIFT            26
0033 #define DIV_CPU_SHIFT           20
0034 #define DIV_DDR_SHIFT           14
0035
0036 #define DIV_DC_WIDTH            4
0037 #define DIV_CPU_WIDTH           4
0038 #define DIV_DDR_WIDTH           4
0039
0040 #define BYPASS_DC_SHIFT         12
0041 #define BYPASS_DDR_SHIFT        10
0042 #define BYPASS_CPU_SHIFT        8
0043
0044 #define BYPASS_DC_WIDTH         1
0045 #define BYPASS_DDR_WIDTH        1
0046 #define BYPASS_CPU_WIDTH        1
0047
0048 #elif defined(CONFIG_LOONGSON1_LS1C)
0049 /* PLL/SDRAM Frequency configuration register Bits */
0050 #define PLL_VALID           BIT(31)
0051 #define FRAC_N              GENMASK(23, 16)
0052 #define RST_TIME            GENMASK(3, 2)
0053 #define SDRAM_DIV           GENMASK(1, 0)
0054
0055 /* CPU/CAMERA/DC Frequency configuration register Bits */
0056 #define DIV_DC_EN           BIT(31)
0057 #define DIV_DC              GENMASK(30, 24)
0058 #define DIV_CAM_EN          BIT(23)
0059 #define DIV_CAM             GENMASK(22, 16)
0060 #define DIV_CPU_EN          BIT(15)
0061 #define DIV_CPU             GENMASK(14, 8)
0062 #define DIV_DC_SEL_EN           BIT(5)
0063 #define DIV_DC_SEL          BIT(4)
0064 #define DIV_CAM_SEL_EN          BIT(3)
0065 #define DIV_CAM_SEL         BIT(2)
0066 #define DIV_CPU_SEL_EN          BIT(1)
0067 #define DIV_CPU_SEL         BIT(0)
0068
0069 #define DIV_DC_SHIFT            24
0070 #define DIV_CAM_SHIFT           16
0071 #define DIV_CPU_SHIFT           8
0072 #define DIV_DDR_SHIFT           0
0073
0074 #define DIV_DC_WIDTH            7
0075 #define DIV_CAM_WIDTH           7
0076 #define DIV_CPU_WIDTH           7
0077 #define DIV_DDR_WIDTH           2
0078
0079 #endif
0080
0081 #endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */