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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2009 Lemote, Inc.
0004  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
0005  */
0006 
0007 #ifndef __ASM_MACH_LOONGSON2EF_LOONGSON_H
0008 #define __ASM_MACH_LOONGSON2EF_LOONGSON_H
0009 
0010 #include <linux/io.h>
0011 #include <linux/init.h>
0012 #include <linux/irq.h>
0013 
0014 /* loongson internal northbridge initialization */
0015 extern void bonito_irq_init(void);
0016 
0017 /* machine-specific reboot/halt operation */
0018 extern void mach_prepare_reboot(void);
0019 extern void mach_prepare_shutdown(void);
0020 
0021 /* environment arguments from bootloader */
0022 extern u32 cpu_clock_freq;
0023 extern u32 memsize, highmemsize;
0024 
0025 /* loongson-specific command line, env and memory initialization */
0026 extern void __init prom_init_memory(void);
0027 extern void __init prom_init_machtype(void);
0028 extern void __init prom_init_env(void);
0029 #ifdef CONFIG_LOONGSON_UART_BASE
0030 extern unsigned long _loongson_uart_base, loongson_uart_base;
0031 extern void prom_init_loongson_uart_base(void);
0032 #endif
0033 
0034 static inline void prom_init_uart_base(void)
0035 {
0036 #ifdef CONFIG_LOONGSON_UART_BASE
0037     prom_init_loongson_uart_base();
0038 #endif
0039 }
0040 
0041 /* irq operation functions */
0042 extern void bonito_irqdispatch(void);
0043 extern void __init bonito_irq_init(void);
0044 extern void __init mach_init_irq(void);
0045 extern void mach_irq_dispatch(unsigned int pending);
0046 extern int mach_i8259_irq(void);
0047 
0048 /* We need this in some places... */
0049 #define delay() ({      \
0050     int x;              \
0051     for (x = 0; x < 100000; x++)    \
0052         __asm__ __volatile__(""); \
0053 })
0054 
0055 #define LOONGSON_REG(x) \
0056     (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
0057 
0058 #define LOONGSON_IRQ_BASE   32
0059 
0060 #define LOONGSON_FLASH_BASE 0x1c000000
0061 #define LOONGSON_FLASH_SIZE 0x02000000  /* 32M */
0062 #define LOONGSON_FLASH_TOP  (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
0063 
0064 #define LOONGSON_LIO0_BASE  0x1e000000
0065 #define LOONGSON_LIO0_SIZE  0x01C00000  /* 28M */
0066 #define LOONGSON_LIO0_TOP   (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
0067 
0068 #define LOONGSON_BOOT_BASE  0x1fc00000
0069 #define LOONGSON_BOOT_SIZE  0x00100000  /* 1M */
0070 #define LOONGSON_BOOT_TOP   (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
0071 #define LOONGSON_REG_BASE   0x1fe00000
0072 #define LOONGSON_REG_SIZE   0x00100000  /* 256Bytes + 256Bytes + ??? */
0073 #define LOONGSON_REG_TOP    (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
0074 
0075 #define LOONGSON_LIO1_BASE  0x1ff00000
0076 #define LOONGSON_LIO1_SIZE  0x00100000  /* 1M */
0077 #define LOONGSON_LIO1_TOP   (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
0078 
0079 #define LOONGSON_PCILO0_BASE    0x10000000
0080 #define LOONGSON_PCILO1_BASE    0x14000000
0081 #define LOONGSON_PCILO2_BASE    0x18000000
0082 #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
0083 #define LOONGSON_PCILO_SIZE 0x0c000000  /* 64M * 3 */
0084 #define LOONGSON_PCILO_TOP  (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
0085 
0086 #define LOONGSON_PCICFG_BASE    0x1fe80000
0087 #define LOONGSON_PCICFG_SIZE    0x00000800  /* 2K */
0088 #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
0089 #define LOONGSON_PCIIO_BASE 0x1fd00000
0090 
0091 #define LOONGSON_PCIIO_SIZE 0x00100000  /* 1M */
0092 #define LOONGSON_PCIIO_TOP  (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
0093 
0094 /* Loongson Register Bases */
0095 
0096 #define LOONGSON_PCICONFIGBASE  0x00
0097 #define LOONGSON_REGBASE    0x100
0098 
0099 /* PCI Configuration Registers */
0100 
0101 #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
0102 #define LOONGSON_PCIDID     LOONGSON_PCI_REG(0x00)
0103 #define LOONGSON_PCICMD     LOONGSON_PCI_REG(0x04)
0104 #define LOONGSON_PCICLASS   LOONGSON_PCI_REG(0x08)
0105 #define LOONGSON_PCILTIMER  LOONGSON_PCI_REG(0x0c)
0106 #define LOONGSON_PCIBASE0   LOONGSON_PCI_REG(0x10)
0107 #define LOONGSON_PCIBASE1   LOONGSON_PCI_REG(0x14)
0108 #define LOONGSON_PCIBASE2   LOONGSON_PCI_REG(0x18)
0109 #define LOONGSON_PCIBASE3   LOONGSON_PCI_REG(0x1c)
0110 #define LOONGSON_PCIBASE4   LOONGSON_PCI_REG(0x20)
0111 #define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
0112 #define LOONGSON_PCIINT     LOONGSON_PCI_REG(0x3c)
0113 
0114 #define LOONGSON_PCI_ISR4C  LOONGSON_PCI_REG(0x4c)
0115 
0116 #define LOONGSON_PCICMD_PERR_CLR    0x80000000
0117 #define LOONGSON_PCICMD_SERR_CLR    0x40000000
0118 #define LOONGSON_PCICMD_MABORT_CLR  0x20000000
0119 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
0120 #define LOONGSON_PCICMD_TABORT_CLR  0x08000000
0121 #define LOONGSON_PCICMD_MPERR_CLR   0x01000000
0122 #define LOONGSON_PCICMD_PERRRESPEN  0x00000040
0123 #define LOONGSON_PCICMD_ASTEPEN     0x00000080
0124 #define LOONGSON_PCICMD_SERREN      0x00000100
0125 #define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
0126 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
0127 
0128 /* Loongson h/w Configuration */
0129 
0130 #define LOONGSON_GENCFG_OFFSET      0x4
0131 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
0132 
0133 #define LOONGSON_GENCFG_DEBUGMODE   0x00000001
0134 #define LOONGSON_GENCFG_SNOOPEN     0x00000002
0135 #define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
0136 
0137 #define LOONGSON_GENCFG_FORCE_IRQA  0x00000008
0138 #define LOONGSON_GENCFG_IRQA_ISOUT  0x00000010
0139 #define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
0140 #define LOONGSON_GENCFG_BYTESWAP    0x00000040
0141 
0142 #define LOONGSON_GENCFG_UNCACHED    0x00000080
0143 #define LOONGSON_GENCFG_PREFETCHEN  0x00000100
0144 #define LOONGSON_GENCFG_WBEHINDEN   0x00000200
0145 #define LOONGSON_GENCFG_CACHEALG    0x00000c00
0146 #define LOONGSON_GENCFG_CACHEALG_SHIFT  10
0147 #define LOONGSON_GENCFG_PCIQUEUE    0x00001000
0148 #define LOONGSON_GENCFG_CACHESTOP   0x00002000
0149 #define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
0150 #define LOONGSON_GENCFG_BUSERREN    0x00008000
0151 #define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
0152 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT    0x00020000
0153 
0154 /* PCI address map control */
0155 
0156 #define LOONGSON_PCIMAP         LOONGSON_REG(LOONGSON_REGBASE + 0x10)
0157 #define LOONGSON_PCIMEMBASECFG      LOONGSON_REG(LOONGSON_REGBASE + 0x14)
0158 #define LOONGSON_PCIMAP_CFG     LOONGSON_REG(LOONGSON_REGBASE + 0x18)
0159 
0160 /* GPIO Regs - r/w */
0161 
0162 #define LOONGSON_GPIODATA       LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
0163 #define LOONGSON_GPIOIE         LOONGSON_REG(LOONGSON_REGBASE + 0x20)
0164 
0165 /* ICU Configuration Regs - r/w */
0166 
0167 #define LOONGSON_INTEDGE        LOONGSON_REG(LOONGSON_REGBASE + 0x24)
0168 #define LOONGSON_INTSTEER       LOONGSON_REG(LOONGSON_REGBASE + 0x28)
0169 #define LOONGSON_INTPOL         LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
0170 
0171 /* ICU Enable Regs - IntEn & IntISR are r/o. */
0172 
0173 #define LOONGSON_INTENSET       LOONGSON_REG(LOONGSON_REGBASE + 0x30)
0174 #define LOONGSON_INTENCLR       LOONGSON_REG(LOONGSON_REGBASE + 0x34)
0175 #define LOONGSON_INTEN          LOONGSON_REG(LOONGSON_REGBASE + 0x38)
0176 #define LOONGSON_INTISR         LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
0177 
0178 /* ICU */
0179 #define LOONGSON_ICU_MBOXES     0x0000000f
0180 #define LOONGSON_ICU_MBOXES_SHIFT   0
0181 #define LOONGSON_ICU_DMARDY     0x00000010
0182 #define LOONGSON_ICU_DMAEMPTY       0x00000020
0183 #define LOONGSON_ICU_COPYRDY        0x00000040
0184 #define LOONGSON_ICU_COPYEMPTY      0x00000080
0185 #define LOONGSON_ICU_COPYERR        0x00000100
0186 #define LOONGSON_ICU_PCIIRQ     0x00000200
0187 #define LOONGSON_ICU_MASTERERR      0x00000400
0188 #define LOONGSON_ICU_SYSTEMERR      0x00000800
0189 #define LOONGSON_ICU_DRAMPERR       0x00001000
0190 #define LOONGSON_ICU_RETRYERR       0x00002000
0191 #define LOONGSON_ICU_GPIOS      0x01ff0000
0192 #define LOONGSON_ICU_GPIOS_SHIFT        16
0193 #define LOONGSON_ICU_GPINS      0x7e000000
0194 #define LOONGSON_ICU_GPINS_SHIFT        25
0195 #define LOONGSON_ICU_MBOX(N)        (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
0196 #define LOONGSON_ICU_GPIO(N)        (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
0197 #define LOONGSON_ICU_GPIN(N)        (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
0198 
0199 /* PCI prefetch window base & mask */
0200 
0201 #define LOONGSON_MEM_WIN_BASE_L     LOONGSON_REG(LOONGSON_REGBASE + 0x40)
0202 #define LOONGSON_MEM_WIN_BASE_H     LOONGSON_REG(LOONGSON_REGBASE + 0x44)
0203 #define LOONGSON_MEM_WIN_MASK_L     LOONGSON_REG(LOONGSON_REGBASE + 0x48)
0204 #define LOONGSON_MEM_WIN_MASK_H     LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
0205 
0206 /* PCI_Hit*_Sel_* */
0207 
0208 #define LOONGSON_PCI_HIT0_SEL_L     LOONGSON_REG(LOONGSON_REGBASE + 0x50)
0209 #define LOONGSON_PCI_HIT0_SEL_H     LOONGSON_REG(LOONGSON_REGBASE + 0x54)
0210 #define LOONGSON_PCI_HIT1_SEL_L     LOONGSON_REG(LOONGSON_REGBASE + 0x58)
0211 #define LOONGSON_PCI_HIT1_SEL_H     LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
0212 #define LOONGSON_PCI_HIT2_SEL_L     LOONGSON_REG(LOONGSON_REGBASE + 0x60)
0213 #define LOONGSON_PCI_HIT2_SEL_H     LOONGSON_REG(LOONGSON_REGBASE + 0x64)
0214 
0215 /* PXArb Config & Status */
0216 
0217 #define LOONGSON_PXARB_CFG      LOONGSON_REG(LOONGSON_REGBASE + 0x68)
0218 #define LOONGSON_PXARB_STATUS       LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
0219 
0220 /* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
0221 #define LOONGSON_CHIPCFG    (void __iomem *)TO_UNCAC(0x1fc00180)
0222 
0223 /* pcimap */
0224 
0225 #define LOONGSON_PCIMAP_PCIMAP_LO0  0x0000003f
0226 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT    0
0227 #define LOONGSON_PCIMAP_PCIMAP_LO1  0x00000fc0
0228 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT    6
0229 #define LOONGSON_PCIMAP_PCIMAP_LO2  0x0003f000
0230 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT    12
0231 #define LOONGSON_PCIMAP_PCIMAP_2    0x00040000
0232 #define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
0233     ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
0234 
0235 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
0236 #include <linux/cpufreq.h>
0237 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
0238 extern int loongson2_cpu_set_rate(unsigned long rate_khz);
0239 #endif
0240 
0241 /*
0242  * address windows configuration module
0243  *
0244  * loongson2e do not have this module
0245  */
0246 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
0247 
0248 /* address window config module base address */
0249 #define LOONGSON_ADDRWINCFG_BASE        0x3ff00000ul
0250 #define LOONGSON_ADDRWINCFG_SIZE        0x180
0251 
0252 extern unsigned long _loongson_addrwincfg_base;
0253 #define LOONGSON_ADDRWINCFG(offset) \
0254     (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
0255 
0256 #define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
0257 #define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
0258 #define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
0259 #define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
0260 
0261 #define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
0262 #define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
0263 #define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
0264 #define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
0265 
0266 #define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
0267 #define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
0268 #define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
0269 #define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
0270 
0271 #define PCIDMA_WIN0_BASE    LOONGSON_ADDRWINCFG(0x60)
0272 #define PCIDMA_WIN1_BASE    LOONGSON_ADDRWINCFG(0x68)
0273 #define PCIDMA_WIN2_BASE    LOONGSON_ADDRWINCFG(0x70)
0274 #define PCIDMA_WIN3_BASE    LOONGSON_ADDRWINCFG(0x78)
0275 
0276 #define PCIDMA_WIN0_MASK    LOONGSON_ADDRWINCFG(0x80)
0277 #define PCIDMA_WIN1_MASK    LOONGSON_ADDRWINCFG(0x88)
0278 #define PCIDMA_WIN2_MASK    LOONGSON_ADDRWINCFG(0x90)
0279 #define PCIDMA_WIN3_MASK    LOONGSON_ADDRWINCFG(0x98)
0280 
0281 #define PCIDMA_WIN0_MMAP    LOONGSON_ADDRWINCFG(0xa0)
0282 #define PCIDMA_WIN1_MMAP    LOONGSON_ADDRWINCFG(0xa8)
0283 #define PCIDMA_WIN2_MMAP    LOONGSON_ADDRWINCFG(0xb0)
0284 #define PCIDMA_WIN3_MMAP    LOONGSON_ADDRWINCFG(0xb8)
0285 
0286 #define ADDRWIN_WIN0    0
0287 #define ADDRWIN_WIN1    1
0288 #define ADDRWIN_WIN2    2
0289 #define ADDRWIN_WIN3    3
0290 
0291 #define ADDRWIN_MAP_DST_DDR 0
0292 #define ADDRWIN_MAP_DST_PCI 1
0293 #define ADDRWIN_MAP_DST_LIO 1
0294 
0295 /*
0296  * s: CPU, PCIDMA
0297  * d: DDR, PCI, LIO
0298  * win: 0, 1, 2, 3
0299  * src: map source
0300  * dst: map destination
0301  * size: ~mask + 1
0302  */
0303 #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
0304     s##_WIN##w##_BASE = (src); \
0305     s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
0306     s##_WIN##w##_MASK = ~(size-1); \
0307 } while (0)
0308 
0309 #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
0310     LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
0311 #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
0312     LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
0313 #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
0314     LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
0315 
0316 #endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
0317 
0318 #endif /* __ASM_MACH_LOONGSON2EF_LOONGSON_H */
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