mach-lantiq/xway/xway_dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  *   Copyright (C) 2011 John Crispin <john@phrozen.org>
0005  */
0006
0007 #ifndef LTQ_DMA_H__
0008 #define LTQ_DMA_H__
0009
0010 #define LTQ_DESC_SIZE       0x08    /* each descriptor is 64bit */
0011 #define LTQ_DESC_NUM        0xC0    /* 192 descriptors / channel */
0012
0013 #define LTQ_DMA_OWN     BIT(31) /* owner bit */
0014 #define LTQ_DMA_C       BIT(30) /* complete bit */
0015 #define LTQ_DMA_SOP     BIT(29) /* start of packet */
0016 #define LTQ_DMA_EOP     BIT(28) /* end of packet */
0017 #define LTQ_DMA_TX_OFFSET(x)    ((x & 0x1f) << 23) /* data bytes offset */
0018 #define LTQ_DMA_RX_OFFSET(x)    ((x & 0x7) << 23) /* data bytes offset */
0019 #define LTQ_DMA_SIZE_MASK   (0xffff) /* the size field is 16 bit */
0020
0021 struct ltq_dma_desc {
0022     u32 ctl;
0023     u32 addr;
0024 };
0025
0026 struct ltq_dma_channel {
0027     int nr;             /* the channel number */
0028     int irq;            /* the mapped irq */
0029     int desc;           /* the current descriptor */
0030     struct ltq_dma_desc *desc_base; /* the descriptor base */
0031     int phys;           /* physical addr */
0032     struct device *dev;
0033 };
0034
0035 enum {
0036     DMA_PORT_ETOP = 0,
0037     DMA_PORT_DEU,
0038 };
0039
0040 extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
0041 extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
0042 extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
0043 extern void ltq_dma_open(struct ltq_dma_channel *ch);
0044 extern void ltq_dma_close(struct ltq_dma_channel *ch);
0045 extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
0046 extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
0047 extern void ltq_dma_free(struct ltq_dma_channel *ch);
0048 extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);
0049
0050 #endif