mach-lantiq/xway/lantiq_soc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
0005  */
0006
0007 #ifndef _LTQ_XWAY_H__
0008 #define _LTQ_XWAY_H__
0009
0010 #ifdef CONFIG_SOC_TYPE_XWAY
0011
0012 #include <lantiq.h>
0013
0014 /* Chip IDs */
0015 #define SOC_ID_DANUBE1      0x129
0016 #define SOC_ID_DANUBE2      0x12B
0017 #define SOC_ID_TWINPASS     0x12D
0018 #define SOC_ID_AMAZON_SE_1  0x152 /* 50601 */
0019 #define SOC_ID_AMAZON_SE_2  0x153 /* 50600 */
0020 #define SOC_ID_ARX188       0x16C
0021 #define SOC_ID_ARX168_1     0x16D
0022 #define SOC_ID_ARX168_2     0x16E
0023 #define SOC_ID_ARX182       0x16F
0024 #define SOC_ID_GRX188       0x170
0025 #define SOC_ID_GRX168       0x171
0026
0027 #define SOC_ID_VRX288       0x1C0 /* v1.1 */
0028 #define SOC_ID_VRX282       0x1C1 /* v1.1 */
0029 #define SOC_ID_VRX268       0x1C2 /* v1.1 */
0030 #define SOC_ID_GRX268       0x1C8 /* v1.1 */
0031 #define SOC_ID_GRX288       0x1C9 /* v1.1 */
0032 #define SOC_ID_VRX288_2     0x00B /* v1.2 */
0033 #define SOC_ID_VRX268_2     0x00C /* v1.2 */
0034 #define SOC_ID_GRX288_2     0x00D /* v1.2 */
0035 #define SOC_ID_GRX282_2     0x00E /* v1.2 */
0036 #define SOC_ID_VRX220       0x000
0037
0038 #define SOC_ID_ARX362       0x004
0039 #define SOC_ID_ARX368       0x005
0040 #define SOC_ID_ARX382       0x007
0041 #define SOC_ID_ARX388       0x008
0042 #define SOC_ID_URX388       0x009
0043 #define SOC_ID_GRX383       0x010
0044 #define SOC_ID_GRX369       0x011
0045 #define SOC_ID_GRX387       0x00F
0046 #define SOC_ID_GRX389       0x012
0047
0048  /* SoC Types */
0049 #define SOC_TYPE_DANUBE     0x01
0050 #define SOC_TYPE_TWINPASS   0x02
0051 #define SOC_TYPE_AR9        0x03
0052 #define SOC_TYPE_VR9        0x04 /* v1.1 */
0053 #define SOC_TYPE_VR9_2      0x05 /* v1.2 */
0054 #define SOC_TYPE_AMAZON_SE  0x06
0055 #define SOC_TYPE_AR10       0x07
0056 #define SOC_TYPE_GRX390     0x08
0057 #define SOC_TYPE_VRX220     0x09
0058
0059 /* BOOT_SEL - find what boot media we have */
0060 #define BS_EXT_ROM      0x0
0061 #define BS_FLASH        0x1
0062 #define BS_MII0         0x2
0063 #define BS_PCI          0x3
0064 #define BS_UART1        0x4
0065 #define BS_SPI          0x5
0066 #define BS_NAND         0x6
0067 #define BS_RMII0        0x7
0068
0069 /* helpers used to access the cgu */
0070 #define ltq_cgu_w32(x, y)   ltq_w32((x), ltq_cgu_membase + (y))
0071 #define ltq_cgu_r32(x)      ltq_r32(ltq_cgu_membase + (x))
0072 extern __iomem void *ltq_cgu_membase;
0073
0074 /*
0075  * during early_printk no ioremap is possible
0076  * let's use KSEG1 instead
0077  */
0078 #define LTQ_ASC1_BASE_ADDR  0x1E100C00
0079 #define LTQ_EARLY_ASC       KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
0080
0081 /* EBU - external bus unit */
0082 #define LTQ_EBU_BUSCON0     0x0060
0083 #define LTQ_EBU_PCC_CON     0x0090
0084 #define LTQ_EBU_PCC_IEN     0x00A4
0085 #define LTQ_EBU_PCC_ISTAT   0x00A0
0086 #define LTQ_EBU_BUSCON1     0x0064
0087 #define LTQ_EBU_ADDRSEL1    0x0024
0088 #define EBU_WRDIS       0x80000000
0089
0090 /* WDT */
0091 #define LTQ_RST_CAUSE_WDTRST    0x20
0092
0093 /* MPS - multi processor unit (voice) */
0094 #define LTQ_MPS_BASE_ADDR   (KSEG1 + 0x1F107000)
0095 #define LTQ_MPS_CHIPID      ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
0096
0097 /* allow booting xrx200 phys */
0098 int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
0099
0100 /* request a non-gpio and set the PIO config */
0101 #define PMU_PPE          BIT(13)
0102 extern void ltq_pmu_enable(unsigned int module);
0103 extern void ltq_pmu_disable(unsigned int module);
0104
0105 #endif /* CONFIG_SOC_TYPE_XWAY */
0106 #endif /* _LTQ_XWAY_H__ */