mach-lantiq/falcon/lantiq_soc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Copyright (C) 2010 John Crispin <john@phrozen.org>
0005  */
0006
0007 #ifndef _LTQ_FALCON_H__
0008 #define _LTQ_FALCON_H__
0009
0010 #ifdef CONFIG_SOC_FALCON
0011
0012 #include <linux/pinctrl/pinctrl.h>
0013 #include <lantiq.h>
0014
0015 /* Chip IDs */
0016 #define SOC_ID_FALCON       0x01B8
0017
0018 /* SoC Types */
0019 #define SOC_TYPE_FALCON     0x01
0020
0021 /*
0022  * during early_printk no ioremap possible at this early stage
0023  * let's use KSEG1 instead
0024  */
0025 #define LTQ_ASC0_BASE_ADDR  0x1E100C00
0026 #define LTQ_EARLY_ASC       KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
0027
0028 /* WDT */
0029 #define LTQ_RST_CAUSE_WDTRST    0x0002
0030
0031 /* CHIP ID */
0032 #define LTQ_STATUS_BASE_ADDR    0x1E802000
0033
0034 #define FALCON_CHIPID       ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
0035 #define FALCON_CHIPTYPE     ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
0036 #define FALCON_CHIPCONF     ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
0037
0038 /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
0039 #define SYSCTL_SYS1     0
0040 #define SYSCTL_SYSETH       1
0041 #define SYSCTL_SYSGPE       2
0042
0043 /* BOOT_SEL - find what boot media we have */
0044 #define BS_FLASH        0x1
0045 #define BS_SPI          0x4
0046
0047 /* global register ranges */
0048 extern __iomem void *ltq_ebu_membase;
0049 extern __iomem void *ltq_sys1_membase;
0050 #define ltq_ebu_w32(x, y)   ltq_w32((x), ltq_ebu_membase + (y))
0051 #define ltq_ebu_r32(x)      ltq_r32(ltq_ebu_membase + (x))
0052
0053 #define ltq_sys1_w32(x, y)  ltq_w32((x), ltq_sys1_membase + (y))
0054 #define ltq_sys1_r32(x)     ltq_r32(ltq_sys1_membase + (x))
0055 #define ltq_sys1_w32_mask(clear, set, reg)   \
0056     ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
0057
0058 /* allow the gpio and pinctrl drivers to talk to eachother */
0059 extern int pinctrl_falcon_get_range_size(int id);
0060 extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
0061
0062 /*
0063  * to keep the irq code generic we need to define this to 0 as falcon
0064  * has no EIU/EBU
0065  */
0066 #define LTQ_EBU_PCC_ISTAT   0
0067
0068 #endif /* CONFIG_SOC_FALCON */
0069 #endif /* _LTQ_XWAY_H__ */