asm/mach-dec/cpu-feature-overrides.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  CPU feature overrides for DECstation systems.  Two variations
0004  *  are generally applicable.
0005  *
0006  *  Copyright (C) 2013  Maciej W. Rozycki
0007  */
0008 #ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
0009 #define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
0010
0011 /* Generic ones first.  */
0012 #define cpu_has_tlb         1
0013 #define cpu_has_tlbinv          0
0014 #define cpu_has_segments        0
0015 #define cpu_has_eva         0
0016 #define cpu_has_htw         0
0017 #define cpu_has_rixiex          0
0018 #define cpu_has_maar            0
0019 #define cpu_has_rw_llb          0
0020 #define cpu_has_divec           0
0021 #define cpu_has_prefetch        0
0022 #define cpu_has_mcheck          0
0023 #define cpu_has_ejtag           0
0024 #define cpu_has_mips16          0
0025 #define cpu_has_mips16e2        0
0026 #define cpu_has_mdmx            0
0027 #define cpu_has_mips3d          0
0028 #define cpu_has_smartmips       0
0029 #define cpu_has_rixi            0
0030 #define cpu_has_xpa         0
0031 #define cpu_has_vtag_icache     0
0032 #define cpu_has_ic_fills_f_dc       0
0033 #define cpu_has_pindexed_dcache     0
0034 #define cpu_icache_snoops_remote_store  1
0035 #define cpu_has_mips_4          0
0036 #define cpu_has_mips_5          0
0037 #define cpu_has_mips32r1        0
0038 #define cpu_has_mips32r2        0
0039 #define cpu_has_mips64r1        0
0040 #define cpu_has_mips64r2        0
0041 #define cpu_has_dsp         0
0042 #define cpu_has_dsp2            0
0043 #define cpu_has_mipsmt          0
0044 #define cpu_has_userlocal       0
0045 #define cpu_has_perf_cntr_intr_bit  0
0046 #define cpu_has_vz          0
0047 #define cpu_has_fre         0
0048 #define cpu_has_cdmm            0
0049
0050 /* R3k-specific ones.  */
0051 #ifdef CONFIG_CPU_R3000
0052 #define cpu_has_3kex            1
0053 #define cpu_has_4kex            0
0054 #define cpu_has_3k_cache        1
0055 #define cpu_has_4k_cache        0
0056 #define cpu_has_32fpr           0
0057 #define cpu_has_counter         0
0058 #define cpu_has_watch           0
0059 #define cpu_has_vce         0
0060 #define cpu_has_cache_cdex_p        0
0061 #define cpu_has_cache_cdex_s        0
0062 #define cpu_has_llsc            0
0063 #define cpu_has_dc_aliases      0
0064 #define cpu_has_mips_2          0
0065 #define cpu_has_mips_3          0
0066 #define cpu_has_nofpuex         1
0067 #define cpu_has_inclusive_pcaches   0
0068 #define cpu_dcache_line_size()      4
0069 #define cpu_icache_line_size()      4
0070 #define cpu_scache_line_size()      0
0071 #endif /* CONFIG_CPU_R3000 */
0072
0073 /* R4k-specific ones.  */
0074 #ifdef CONFIG_CPU_R4X00
0075 #define cpu_has_3kex            0
0076 #define cpu_has_4kex            1
0077 #define cpu_has_3k_cache        0
0078 #define cpu_has_4k_cache        1
0079 #define cpu_has_32fpr           1
0080 #define cpu_has_counter         1
0081 #define cpu_has_watch           1
0082 #define cpu_has_vce         1
0083 #define cpu_has_cache_cdex_p        1
0084 #define cpu_has_cache_cdex_s        1
0085 #define cpu_has_llsc            1
0086 #define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
0087 #define cpu_has_mips_2          1
0088 #define cpu_has_mips_3          1
0089 #define cpu_has_nofpuex         0
0090 #define cpu_has_inclusive_pcaches   1
0091 #define cpu_dcache_line_size()      16
0092 #define cpu_icache_line_size()      16
0093 #define cpu_scache_line_size()      32
0094 #endif /* CONFIG_CPU_R4X00 */
0095
0096 #endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */