asm/mach-cobalt/irq.h

0001 /*
0002  * Cobalt IRQ definitions.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 1997 Cobalt Microserver
0009  * Copyright (C) 1997, 2003 Ralf Baechle
0010  * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
0011  * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
0012  */
0013 #ifndef _ASM_COBALT_IRQ_H
0014 #define _ASM_COBALT_IRQ_H
0015
0016 /*
0017  * i8259 interrupts used on Cobalt:
0018  *
0019  *  8  - RTC
0020  *  9  - PCI slot
0021  *  14 - IDE0
0022  *  15 - IDE1(no connector on board)
0023  */
0024 #define I8259A_IRQ_BASE         0
0025
0026 #define PCISLOT_IRQ         (I8259A_IRQ_BASE + 9)
0027
0028 /*
0029  * CPU interrupts used on Cobalt:
0030  *
0031  *  0 - Software interrupt 0 (unused)
0032  *  1 - Software interrupt 0 (unused)
0033  *  2 - cascade GT64111
0034  *  3 - ethernet or SCSI host controller
0035  *  4 - ethernet
0036  *  5 - 16550 UART
0037  *  6 - cascade i8259
0038  *  7 - CP0 counter
0039  */
0040 #define MIPS_CPU_IRQ_BASE       16
0041
0042 #define GT641XX_CASCADE_IRQ     (MIPS_CPU_IRQ_BASE + 2)
0043 #define RAQ2_SCSI_IRQ           (MIPS_CPU_IRQ_BASE + 3)
0044 #define ETH0_IRQ            (MIPS_CPU_IRQ_BASE + 3)
0045 #define QUBE1_ETH0_IRQ          (MIPS_CPU_IRQ_BASE + 4)
0046 #define ETH1_IRQ            (MIPS_CPU_IRQ_BASE + 4)
0047 #define SERIAL_IRQ          (MIPS_CPU_IRQ_BASE + 5)
0048 #define SCSI_IRQ            (MIPS_CPU_IRQ_BASE + 5)
0049 #define I8259_CASCADE_IRQ       (MIPS_CPU_IRQ_BASE + 6)
0050
0051 #define GT641XX_IRQ_BASE        24
0052
0053 #include <asm/irq_gt641xx.h>
0054
0055 #define NR_IRQS                 (GT641XX_PCI_INT3_IRQ + 1)
0056
0057 #endif /* _ASM_COBALT_IRQ_H */