asm/mach-cavium-octeon/irq.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2004-2008 Cavium Networks
0007  */
0008 #ifndef __OCTEON_IRQ_H__
0009 #define __OCTEON_IRQ_H__
0010
0011 #define NR_IRQS OCTEON_IRQ_LAST
0012 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
0013
0014 enum octeon_irq {
0015 /* 1 - 8 represent the 8 MIPS standard interrupt sources */
0016     OCTEON_IRQ_SW0 = 1,
0017     OCTEON_IRQ_SW1,
0018 /* CIU0, CUI2, CIU4 are 3, 4, 5 */
0019     OCTEON_IRQ_5 = 6,
0020     OCTEON_IRQ_PERF,
0021     OCTEON_IRQ_TIMER,
0022 /* sources in CIU_INTX_EN0 */
0023     OCTEON_IRQ_WORKQ0,
0024     OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
0025     OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
0026     OCTEON_IRQ_MBOX1,
0027     OCTEON_IRQ_MBOX2,
0028     OCTEON_IRQ_MBOX3,
0029     OCTEON_IRQ_PCI_INT0,
0030     OCTEON_IRQ_PCI_INT1,
0031     OCTEON_IRQ_PCI_INT2,
0032     OCTEON_IRQ_PCI_INT3,
0033     OCTEON_IRQ_PCI_MSI0,
0034     OCTEON_IRQ_PCI_MSI1,
0035     OCTEON_IRQ_PCI_MSI2,
0036     OCTEON_IRQ_PCI_MSI3,
0037
0038     OCTEON_IRQ_TWSI,
0039     OCTEON_IRQ_TWSI2,
0040     OCTEON_IRQ_RML,
0041     OCTEON_IRQ_TIMER0,
0042     OCTEON_IRQ_TIMER1,
0043     OCTEON_IRQ_TIMER2,
0044     OCTEON_IRQ_TIMER3,
0045 #ifndef CONFIG_PCI_MSI
0046     OCTEON_IRQ_LAST = 127
0047 #endif
0048 };
0049
0050 #ifdef CONFIG_PCI_MSI
0051 /* 256 - 511 represent the MSI interrupts 0-255 */
0052 #define OCTEON_IRQ_MSI_BIT0 (256)
0053
0054 #define OCTEON_IRQ_MSI_LAST  (OCTEON_IRQ_MSI_BIT0 + 255)
0055 #define OCTEON_IRQ_LAST      (OCTEON_IRQ_MSI_LAST + 1)
0056 #endif
0057
0058 #endif