asm/mach-cavium-octeon/cpu-feature-overrides.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2004 Cavium Networks
0007  */
0008 #ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
0009 #define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
0010
0011 #include <linux/types.h>
0012 #include <asm/mipsregs.h>
0013
0014 /*
0015  * Cavium Octeons are MIPS64v2 processors
0016  */
0017 #define cpu_dcache_line_size()  128
0018 #define cpu_icache_line_size()  128
0019
0020
0021 #define cpu_has_4kex        1
0022 #define cpu_has_3k_cache    0
0023 #define cpu_has_4k_cache    0
0024 #define cpu_has_counter     1
0025 #define cpu_has_watch       1
0026 #define cpu_has_divec       1
0027 #define cpu_has_vce     0
0028 #define cpu_has_cache_cdex_p    0
0029 #define cpu_has_cache_cdex_s    0
0030 #define cpu_has_prefetch    1
0031
0032 #define cpu_has_llsc        1
0033 /*
0034  * We Disable LL/SC on non SMP systems as it is faster to disable
0035  * interrupts for atomic access than a LL/SC.
0036  */
0037 #ifdef CONFIG_SMP
0038 # define kernel_uses_llsc   1
0039 #else
0040 # define kernel_uses_llsc   0
0041 #endif
0042 #define cpu_has_vtag_icache 1
0043 #define cpu_has_dc_aliases  0
0044 #define cpu_has_ic_fills_f_dc   0
0045 #define cpu_has_64bits      1
0046 #define cpu_has_octeon_cache    1
0047 #define cpu_has_mips32r1    1
0048 #define cpu_has_mips32r2    1
0049 #define cpu_has_mips64r1    1
0050 #define cpu_has_mips64r2    1
0051 #define cpu_has_dsp     0
0052 #define cpu_has_dsp2        0
0053 #define cpu_has_mipsmt      0
0054 #define cpu_has_vint        0
0055 #define cpu_has_veic        0
0056 #define cpu_hwrena_impl_bits    (MIPS_HWRENA_IMPL1 | MIPS_HWRENA_IMPL2)
0057 #define cpu_has_wsbh            1
0058
0059 #define cpu_has_rixi        (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
0060
0061 #define ARCH_HAS_SPINLOCK_PREFETCH 1
0062 #define spin_lock_prefetch(x) prefetch(x)
0063 #define PREFETCH_STRIDE 128
0064
0065 #ifdef __OCTEON__
0066 /*
0067  * All gcc versions that have OCTEON support define __OCTEON__ and have the
0068  *  __builtin_popcount support.
0069  */
0070 #define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
0071 #endif
0072
0073 /*
0074  * The last 256MB are reserved for device to device mappings and the
0075  * BAR1 hole.
0076  */
0077 #define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
0078
0079 #endif