asm/mach-bcm63xx/bcm63xx_dev_enet.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef BCM63XX_DEV_ENET_H_
0003 #define BCM63XX_DEV_ENET_H_
0004
0005 #include <linux/if_ether.h>
0006 #include <linux/init.h>
0007
0008 #include <bcm63xx_regs.h>
0009
0010 /*
0011  * on board ethernet platform data
0012  */
0013 struct bcm63xx_enet_platform_data {
0014     char mac_addr[ETH_ALEN];
0015
0016     int has_phy;
0017
0018     /* if has_phy, then set use_internal_phy */
0019     int use_internal_phy;
0020
0021     /* or fill phy info to use an external one */
0022     int phy_id;
0023     int has_phy_interrupt;
0024     int phy_interrupt;
0025
0026     /* if has_phy, use autonegotiated pause parameters or force
0027      * them */
0028     int pause_auto;
0029     int pause_rx;
0030     int pause_tx;
0031
0032     /* if !has_phy, set desired forced speed/duplex */
0033     int force_speed_100;
0034     int force_duplex_full;
0035
0036     /* if !has_phy, set callback to perform mii device
0037      * init/remove */
0038     int (*mii_config)(struct net_device *dev, int probe,
0039               int (*mii_read)(struct net_device *dev,
0040                       int phy_id, int reg),
0041               void (*mii_write)(struct net_device *dev,
0042                         int phy_id, int reg, int val));
0043
0044     /* DMA channel enable mask */
0045     u32 dma_chan_en_mask;
0046
0047     /* DMA channel interrupt mask */
0048     u32 dma_chan_int_mask;
0049
0050     /* DMA engine has internal SRAM */
0051     bool dma_has_sram;
0052
0053     /* DMA channel register width */
0054     unsigned int dma_chan_width;
0055
0056     /* DMA descriptor shift */
0057     unsigned int dma_desc_shift;
0058
0059     /* dma channel ids */
0060     int rx_chan;
0061     int tx_chan;
0062 };
0063
0064 /*
0065  * on board ethernet switch platform data
0066  */
0067 #define ENETSW_MAX_PORT 8
0068 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
0069 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
0070
0071 #define ENETSW_RGMII_PORT0  4
0072
0073 struct bcm63xx_enetsw_port {
0074     int     used;
0075     int     phy_id;
0076
0077     int     bypass_link;
0078     int     force_speed;
0079     int     force_duplex_full;
0080
0081     const char  *name;
0082 };
0083
0084 struct bcm63xx_enetsw_platform_data {
0085     char mac_addr[ETH_ALEN];
0086     int num_ports;
0087     struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
0088
0089     /* DMA channel enable mask */
0090     u32 dma_chan_en_mask;
0091
0092     /* DMA channel interrupt mask */
0093     u32 dma_chan_int_mask;
0094
0095     /* DMA channel register width */
0096     unsigned int dma_chan_width;
0097
0098     /* DMA engine has internal SRAM */
0099     bool dma_has_sram;
0100 };
0101
0102 int __init bcm63xx_enet_register(int unit,
0103                  const struct bcm63xx_enet_platform_data *pd);
0104
0105 int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
0106
0107 enum bcm63xx_regs_enetdmac {
0108     ENETDMAC_CHANCFG,
0109     ENETDMAC_IR,
0110     ENETDMAC_IRMASK,
0111     ENETDMAC_MAXBURST,
0112     ENETDMAC_BUFALLOC,
0113     ENETDMAC_RSTART,
0114     ENETDMAC_FC,
0115     ENETDMAC_LEN,
0116 };
0117
0118 static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
0119 {
0120     extern const unsigned long *bcm63xx_regs_enetdmac;
0121
0122     return bcm63xx_regs_enetdmac[reg];
0123 }
0124
0125
0126 #endif /* ! BCM63XX_DEV_ENET_H_ */