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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef BCM63XX_CPU_H_
0003 #define BCM63XX_CPU_H_
0004 
0005 #include <linux/types.h>
0006 #include <linux/init.h>
0007 
0008 /*
0009  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
0010  * compile time if only one CPU support is enabled (idea stolen from
0011  * arm mach-types)
0012  */
0013 #define BCM3368_CPU_ID      0x3368
0014 #define BCM6328_CPU_ID      0x6328
0015 #define BCM6338_CPU_ID      0x6338
0016 #define BCM6345_CPU_ID      0x6345
0017 #define BCM6348_CPU_ID      0x6348
0018 #define BCM6358_CPU_ID      0x6358
0019 #define BCM6362_CPU_ID      0x6362
0020 #define BCM6368_CPU_ID      0x6368
0021 
0022 void __init bcm63xx_cpu_init(void);
0023 u8 bcm63xx_get_cpu_rev(void);
0024 unsigned int bcm63xx_get_cpu_freq(void);
0025 
0026 static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
0027 {
0028     switch (cpu_id) {
0029 #ifdef CONFIG_BCM63XX_CPU_3368
0030         case BCM3368_CPU_ID:
0031 #endif
0032 
0033 #ifdef CONFIG_BCM63XX_CPU_6328
0034         case BCM6328_CPU_ID:
0035 #endif
0036 
0037 #ifdef CONFIG_BCM63XX_CPU_6338
0038         case BCM6338_CPU_ID:
0039 #endif
0040 
0041 #ifdef CONFIG_BCM63XX_CPU_6345
0042         case BCM6345_CPU_ID:
0043 #endif
0044 
0045 #ifdef CONFIG_BCM63XX_CPU_6348
0046         case BCM6348_CPU_ID:
0047 #endif
0048 
0049 #ifdef CONFIG_BCM63XX_CPU_6358
0050         case BCM6358_CPU_ID:
0051 #endif
0052 
0053 #ifdef CONFIG_BCM63XX_CPU_6362
0054         case BCM6362_CPU_ID:
0055 #endif
0056 
0057 #ifdef CONFIG_BCM63XX_CPU_6368
0058         case BCM6368_CPU_ID:
0059 #endif
0060         break;
0061     default:
0062         unreachable();
0063     }
0064 
0065     return cpu_id;
0066 }
0067 
0068 extern u16 bcm63xx_cpu_id;
0069 
0070 static inline u16 __pure bcm63xx_get_cpu_id(void)
0071 {
0072     const u16 cpu_id = bcm63xx_cpu_id;
0073 
0074     return __bcm63xx_get_cpu_id(cpu_id);
0075 }
0076 
0077 #define BCMCPU_IS_3368()    (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
0078 #define BCMCPU_IS_6328()    (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
0079 #define BCMCPU_IS_6338()    (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
0080 #define BCMCPU_IS_6345()    (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
0081 #define BCMCPU_IS_6348()    (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
0082 #define BCMCPU_IS_6358()    (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
0083 #define BCMCPU_IS_6362()    (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
0084 #define BCMCPU_IS_6368()    (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
0085 
0086 /*
0087  * While registers sets are (mostly) the same across 63xx CPU, base
0088  * address of these sets do change.
0089  */
0090 enum bcm63xx_regs_set {
0091     RSET_DSL_LMEM = 0,
0092     RSET_PERF,
0093     RSET_TIMER,
0094     RSET_WDT,
0095     RSET_UART0,
0096     RSET_UART1,
0097     RSET_GPIO,
0098     RSET_SPI,
0099     RSET_HSSPI,
0100     RSET_UDC0,
0101     RSET_OHCI0,
0102     RSET_OHCI_PRIV,
0103     RSET_USBH_PRIV,
0104     RSET_USBD,
0105     RSET_USBDMA,
0106     RSET_MPI,
0107     RSET_PCMCIA,
0108     RSET_PCIE,
0109     RSET_DSL,
0110     RSET_ENET0,
0111     RSET_ENET1,
0112     RSET_ENETDMA,
0113     RSET_ENETDMAC,
0114     RSET_ENETDMAS,
0115     RSET_ENETSW,
0116     RSET_EHCI0,
0117     RSET_SDRAM,
0118     RSET_MEMC,
0119     RSET_DDR,
0120     RSET_M2M,
0121     RSET_ATM,
0122     RSET_XTM,
0123     RSET_XTMDMA,
0124     RSET_XTMDMAC,
0125     RSET_XTMDMAS,
0126     RSET_PCM,
0127     RSET_PCMDMA,
0128     RSET_PCMDMAC,
0129     RSET_PCMDMAS,
0130     RSET_RNG,
0131     RSET_MISC
0132 };
0133 
0134 #define RSET_DSL_LMEM_SIZE      (64 * 1024 * 4)
0135 #define RSET_DSL_SIZE           4096
0136 #define RSET_WDT_SIZE           12
0137 #define BCM_6338_RSET_SPI_SIZE      64
0138 #define BCM_6348_RSET_SPI_SIZE      64
0139 #define BCM_6358_RSET_SPI_SIZE      1804
0140 #define BCM_6368_RSET_SPI_SIZE      1804
0141 #define RSET_ENET_SIZE          2048
0142 #define RSET_ENETDMA_SIZE       256
0143 #define RSET_6345_ENETDMA_SIZE      64
0144 #define RSET_ENETDMAC_SIZE(chans)   (16 * (chans))
0145 #define RSET_ENETDMAS_SIZE(chans)   (16 * (chans))
0146 #define RSET_ENETSW_SIZE        65536
0147 #define RSET_UART_SIZE          24
0148 #define RSET_HSSPI_SIZE         1536
0149 #define RSET_UDC_SIZE           256
0150 #define RSET_OHCI_SIZE          256
0151 #define RSET_EHCI_SIZE          256
0152 #define RSET_USBD_SIZE          256
0153 #define RSET_USBDMA_SIZE        1280
0154 #define RSET_PCMCIA_SIZE        12
0155 #define RSET_M2M_SIZE           256
0156 #define RSET_ATM_SIZE           4096
0157 #define RSET_XTM_SIZE           10240
0158 #define RSET_XTMDMA_SIZE        256
0159 #define RSET_XTMDMAC_SIZE(chans)    (16 * (chans))
0160 #define RSET_XTMDMAS_SIZE(chans)    (16 * (chans))
0161 #define RSET_RNG_SIZE           20
0162 
0163 /*
0164  * 3368 register sets base address
0165  */
0166 #define BCM_3368_DSL_LMEM_BASE      (0xdeadbeef)
0167 #define BCM_3368_PERF_BASE      (0xfff8c000)
0168 #define BCM_3368_TIMER_BASE     (0xfff8c040)
0169 #define BCM_3368_WDT_BASE       (0xfff8c080)
0170 #define BCM_3368_UART0_BASE     (0xfff8c100)
0171 #define BCM_3368_UART1_BASE     (0xfff8c120)
0172 #define BCM_3368_GPIO_BASE      (0xfff8c080)
0173 #define BCM_3368_SPI_BASE       (0xfff8c800)
0174 #define BCM_3368_HSSPI_BASE     (0xdeadbeef)
0175 #define BCM_3368_UDC0_BASE      (0xdeadbeef)
0176 #define BCM_3368_USBDMA_BASE        (0xdeadbeef)
0177 #define BCM_3368_OHCI0_BASE     (0xdeadbeef)
0178 #define BCM_3368_OHCI_PRIV_BASE     (0xdeadbeef)
0179 #define BCM_3368_USBH_PRIV_BASE     (0xdeadbeef)
0180 #define BCM_3368_USBD_BASE      (0xdeadbeef)
0181 #define BCM_3368_MPI_BASE       (0xfff80000)
0182 #define BCM_3368_PCMCIA_BASE        (0xfff80054)
0183 #define BCM_3368_PCIE_BASE      (0xdeadbeef)
0184 #define BCM_3368_SDRAM_REGS_BASE    (0xdeadbeef)
0185 #define BCM_3368_DSL_BASE       (0xdeadbeef)
0186 #define BCM_3368_UBUS_BASE      (0xdeadbeef)
0187 #define BCM_3368_ENET0_BASE     (0xfff98000)
0188 #define BCM_3368_ENET1_BASE     (0xfff98800)
0189 #define BCM_3368_ENETDMA_BASE       (0xfff99800)
0190 #define BCM_3368_ENETDMAC_BASE      (0xfff99900)
0191 #define BCM_3368_ENETDMAS_BASE      (0xfff99a00)
0192 #define BCM_3368_ENETSW_BASE        (0xdeadbeef)
0193 #define BCM_3368_EHCI0_BASE     (0xdeadbeef)
0194 #define BCM_3368_SDRAM_BASE     (0xdeadbeef)
0195 #define BCM_3368_MEMC_BASE      (0xfff84000)
0196 #define BCM_3368_DDR_BASE       (0xdeadbeef)
0197 #define BCM_3368_M2M_BASE       (0xdeadbeef)
0198 #define BCM_3368_ATM_BASE       (0xdeadbeef)
0199 #define BCM_3368_XTM_BASE       (0xdeadbeef)
0200 #define BCM_3368_XTMDMA_BASE        (0xdeadbeef)
0201 #define BCM_3368_XTMDMAC_BASE       (0xdeadbeef)
0202 #define BCM_3368_XTMDMAS_BASE       (0xdeadbeef)
0203 #define BCM_3368_PCM_BASE       (0xfff9c200)
0204 #define BCM_3368_PCMDMA_BASE        (0xdeadbeef)
0205 #define BCM_3368_PCMDMAC_BASE       (0xdeadbeef)
0206 #define BCM_3368_PCMDMAS_BASE       (0xdeadbeef)
0207 #define BCM_3368_RNG_BASE       (0xdeadbeef)
0208 #define BCM_3368_MISC_BASE      (0xdeadbeef)
0209 
0210 /*
0211  * 6328 register sets base address
0212  */
0213 #define BCM_6328_DSL_LMEM_BASE      (0xdeadbeef)
0214 #define BCM_6328_PERF_BASE      (0xb0000000)
0215 #define BCM_6328_TIMER_BASE     (0xb0000040)
0216 #define BCM_6328_WDT_BASE       (0xb000005c)
0217 #define BCM_6328_UART0_BASE     (0xb0000100)
0218 #define BCM_6328_UART1_BASE     (0xb0000120)
0219 #define BCM_6328_GPIO_BASE      (0xb0000080)
0220 #define BCM_6328_SPI_BASE       (0xdeadbeef)
0221 #define BCM_6328_HSSPI_BASE     (0xb0001000)
0222 #define BCM_6328_UDC0_BASE      (0xdeadbeef)
0223 #define BCM_6328_USBDMA_BASE        (0xb000c000)
0224 #define BCM_6328_OHCI0_BASE     (0xb0002600)
0225 #define BCM_6328_OHCI_PRIV_BASE     (0xdeadbeef)
0226 #define BCM_6328_USBH_PRIV_BASE     (0xb0002700)
0227 #define BCM_6328_USBD_BASE      (0xb0002400)
0228 #define BCM_6328_MPI_BASE       (0xdeadbeef)
0229 #define BCM_6328_PCMCIA_BASE        (0xdeadbeef)
0230 #define BCM_6328_PCIE_BASE      (0xb0e40000)
0231 #define BCM_6328_SDRAM_REGS_BASE    (0xdeadbeef)
0232 #define BCM_6328_DSL_BASE       (0xb0001900)
0233 #define BCM_6328_UBUS_BASE      (0xdeadbeef)
0234 #define BCM_6328_ENET0_BASE     (0xdeadbeef)
0235 #define BCM_6328_ENET1_BASE     (0xdeadbeef)
0236 #define BCM_6328_ENETDMA_BASE       (0xb000d800)
0237 #define BCM_6328_ENETDMAC_BASE      (0xb000da00)
0238 #define BCM_6328_ENETDMAS_BASE      (0xb000dc00)
0239 #define BCM_6328_ENETSW_BASE        (0xb0e00000)
0240 #define BCM_6328_EHCI0_BASE     (0xb0002500)
0241 #define BCM_6328_SDRAM_BASE     (0xdeadbeef)
0242 #define BCM_6328_MEMC_BASE      (0xdeadbeef)
0243 #define BCM_6328_DDR_BASE       (0xb0003000)
0244 #define BCM_6328_M2M_BASE       (0xdeadbeef)
0245 #define BCM_6328_ATM_BASE       (0xdeadbeef)
0246 #define BCM_6328_XTM_BASE       (0xdeadbeef)
0247 #define BCM_6328_XTMDMA_BASE        (0xb000b800)
0248 #define BCM_6328_XTMDMAC_BASE       (0xdeadbeef)
0249 #define BCM_6328_XTMDMAS_BASE       (0xdeadbeef)
0250 #define BCM_6328_PCM_BASE       (0xb000a800)
0251 #define BCM_6328_PCMDMA_BASE        (0xdeadbeef)
0252 #define BCM_6328_PCMDMAC_BASE       (0xdeadbeef)
0253 #define BCM_6328_PCMDMAS_BASE       (0xdeadbeef)
0254 #define BCM_6328_RNG_BASE       (0xdeadbeef)
0255 #define BCM_6328_MISC_BASE      (0xb0001800)
0256 #define BCM_6328_OTP_BASE       (0xb0000600)
0257 
0258 /*
0259  * 6338 register sets base address
0260  */
0261 #define BCM_6338_DSL_LMEM_BASE      (0xfff00000)
0262 #define BCM_6338_PERF_BASE      (0xfffe0000)
0263 #define BCM_6338_BB_BASE        (0xfffe0100)
0264 #define BCM_6338_TIMER_BASE     (0xfffe0200)
0265 #define BCM_6338_WDT_BASE       (0xfffe021c)
0266 #define BCM_6338_UART0_BASE     (0xfffe0300)
0267 #define BCM_6338_UART1_BASE     (0xdeadbeef)
0268 #define BCM_6338_GPIO_BASE      (0xfffe0400)
0269 #define BCM_6338_SPI_BASE       (0xfffe0c00)
0270 #define BCM_6338_HSSPI_BASE     (0xdeadbeef)
0271 #define BCM_6338_UDC0_BASE      (0xdeadbeef)
0272 #define BCM_6338_USBDMA_BASE        (0xfffe2400)
0273 #define BCM_6338_OHCI0_BASE     (0xdeadbeef)
0274 #define BCM_6338_OHCI_PRIV_BASE     (0xfffe3000)
0275 #define BCM_6338_USBH_PRIV_BASE     (0xdeadbeef)
0276 #define BCM_6338_USBD_BASE      (0xdeadbeef)
0277 #define BCM_6338_MPI_BASE       (0xfffe3160)
0278 #define BCM_6338_PCMCIA_BASE        (0xdeadbeef)
0279 #define BCM_6338_PCIE_BASE      (0xdeadbeef)
0280 #define BCM_6338_SDRAM_REGS_BASE    (0xfffe3100)
0281 #define BCM_6338_DSL_BASE       (0xfffe1000)
0282 #define BCM_6338_UBUS_BASE      (0xdeadbeef)
0283 #define BCM_6338_ENET0_BASE     (0xfffe2800)
0284 #define BCM_6338_ENET1_BASE     (0xdeadbeef)
0285 #define BCM_6338_ENETDMA_BASE       (0xfffe2400)
0286 #define BCM_6338_ENETDMAC_BASE      (0xfffe2500)
0287 #define BCM_6338_ENETDMAS_BASE      (0xfffe2600)
0288 #define BCM_6338_ENETSW_BASE        (0xdeadbeef)
0289 #define BCM_6338_EHCI0_BASE     (0xdeadbeef)
0290 #define BCM_6338_SDRAM_BASE     (0xfffe3100)
0291 #define BCM_6338_MEMC_BASE      (0xdeadbeef)
0292 #define BCM_6338_DDR_BASE       (0xdeadbeef)
0293 #define BCM_6338_M2M_BASE       (0xdeadbeef)
0294 #define BCM_6338_ATM_BASE       (0xfffe2000)
0295 #define BCM_6338_XTM_BASE       (0xdeadbeef)
0296 #define BCM_6338_XTMDMA_BASE        (0xdeadbeef)
0297 #define BCM_6338_XTMDMAC_BASE       (0xdeadbeef)
0298 #define BCM_6338_XTMDMAS_BASE       (0xdeadbeef)
0299 #define BCM_6338_PCM_BASE       (0xdeadbeef)
0300 #define BCM_6338_PCMDMA_BASE        (0xdeadbeef)
0301 #define BCM_6338_PCMDMAC_BASE       (0xdeadbeef)
0302 #define BCM_6338_PCMDMAS_BASE       (0xdeadbeef)
0303 #define BCM_6338_RNG_BASE       (0xdeadbeef)
0304 #define BCM_6338_MISC_BASE      (0xdeadbeef)
0305 
0306 /*
0307  * 6345 register sets base address
0308  */
0309 #define BCM_6345_DSL_LMEM_BASE      (0xfff00000)
0310 #define BCM_6345_PERF_BASE      (0xfffe0000)
0311 #define BCM_6345_BB_BASE        (0xfffe0100)
0312 #define BCM_6345_TIMER_BASE     (0xfffe0200)
0313 #define BCM_6345_WDT_BASE       (0xfffe021c)
0314 #define BCM_6345_UART0_BASE     (0xfffe0300)
0315 #define BCM_6345_UART1_BASE     (0xdeadbeef)
0316 #define BCM_6345_GPIO_BASE      (0xfffe0400)
0317 #define BCM_6345_SPI_BASE       (0xdeadbeef)
0318 #define BCM_6345_HSSPI_BASE     (0xdeadbeef)
0319 #define BCM_6345_UDC0_BASE      (0xdeadbeef)
0320 #define BCM_6345_USBDMA_BASE        (0xfffe2800)
0321 #define BCM_6345_ENET0_BASE     (0xfffe1800)
0322 #define BCM_6345_ENETDMA_BASE       (0xfffe2800)
0323 #define BCM_6345_ENETDMAC_BASE      (0xfffe2840)
0324 #define BCM_6345_ENETDMAS_BASE      (0xfffe2a00)
0325 #define BCM_6345_ENETSW_BASE        (0xdeadbeef)
0326 #define BCM_6345_PCMCIA_BASE        (0xfffe2028)
0327 #define BCM_6345_MPI_BASE       (0xfffe2000)
0328 #define BCM_6345_PCIE_BASE      (0xdeadbeef)
0329 #define BCM_6345_OHCI0_BASE     (0xfffe2100)
0330 #define BCM_6345_OHCI_PRIV_BASE     (0xfffe2200)
0331 #define BCM_6345_USBH_PRIV_BASE     (0xdeadbeef)
0332 #define BCM_6345_USBD_BASE      (0xdeadbeef)
0333 #define BCM_6345_SDRAM_REGS_BASE    (0xfffe2300)
0334 #define BCM_6345_DSL_BASE       (0xdeadbeef)
0335 #define BCM_6345_UBUS_BASE      (0xdeadbeef)
0336 #define BCM_6345_ENET1_BASE     (0xdeadbeef)
0337 #define BCM_6345_EHCI0_BASE     (0xdeadbeef)
0338 #define BCM_6345_SDRAM_BASE     (0xfffe2300)
0339 #define BCM_6345_MEMC_BASE      (0xdeadbeef)
0340 #define BCM_6345_DDR_BASE       (0xdeadbeef)
0341 #define BCM_6345_M2M_BASE       (0xdeadbeef)
0342 #define BCM_6345_ATM_BASE       (0xfffe4000)
0343 #define BCM_6345_XTM_BASE       (0xdeadbeef)
0344 #define BCM_6345_XTMDMA_BASE        (0xdeadbeef)
0345 #define BCM_6345_XTMDMAC_BASE       (0xdeadbeef)
0346 #define BCM_6345_XTMDMAS_BASE       (0xdeadbeef)
0347 #define BCM_6345_PCM_BASE       (0xdeadbeef)
0348 #define BCM_6345_PCMDMA_BASE        (0xdeadbeef)
0349 #define BCM_6345_PCMDMAC_BASE       (0xdeadbeef)
0350 #define BCM_6345_PCMDMAS_BASE       (0xdeadbeef)
0351 #define BCM_6345_RNG_BASE       (0xdeadbeef)
0352 #define BCM_6345_MISC_BASE      (0xdeadbeef)
0353 
0354 /*
0355  * 6348 register sets base address
0356  */
0357 #define BCM_6348_DSL_LMEM_BASE      (0xfff00000)
0358 #define BCM_6348_PERF_BASE      (0xfffe0000)
0359 #define BCM_6348_TIMER_BASE     (0xfffe0200)
0360 #define BCM_6348_WDT_BASE       (0xfffe021c)
0361 #define BCM_6348_UART0_BASE     (0xfffe0300)
0362 #define BCM_6348_UART1_BASE     (0xdeadbeef)
0363 #define BCM_6348_GPIO_BASE      (0xfffe0400)
0364 #define BCM_6348_SPI_BASE       (0xfffe0c00)
0365 #define BCM_6348_HSSPI_BASE     (0xdeadbeef)
0366 #define BCM_6348_UDC0_BASE      (0xfffe1000)
0367 #define BCM_6348_USBDMA_BASE        (0xdeadbeef)
0368 #define BCM_6348_OHCI0_BASE     (0xfffe1b00)
0369 #define BCM_6348_OHCI_PRIV_BASE     (0xfffe1c00)
0370 #define BCM_6348_USBH_PRIV_BASE     (0xdeadbeef)
0371 #define BCM_6348_USBD_BASE      (0xdeadbeef)
0372 #define BCM_6348_MPI_BASE       (0xfffe2000)
0373 #define BCM_6348_PCMCIA_BASE        (0xfffe2054)
0374 #define BCM_6348_PCIE_BASE      (0xdeadbeef)
0375 #define BCM_6348_SDRAM_REGS_BASE    (0xfffe2300)
0376 #define BCM_6348_M2M_BASE       (0xfffe2800)
0377 #define BCM_6348_DSL_BASE       (0xfffe3000)
0378 #define BCM_6348_ENET0_BASE     (0xfffe6000)
0379 #define BCM_6348_ENET1_BASE     (0xfffe6800)
0380 #define BCM_6348_ENETDMA_BASE       (0xfffe7000)
0381 #define BCM_6348_ENETDMAC_BASE      (0xfffe7100)
0382 #define BCM_6348_ENETDMAS_BASE      (0xfffe7200)
0383 #define BCM_6348_ENETSW_BASE        (0xdeadbeef)
0384 #define BCM_6348_EHCI0_BASE     (0xdeadbeef)
0385 #define BCM_6348_SDRAM_BASE     (0xfffe2300)
0386 #define BCM_6348_MEMC_BASE      (0xdeadbeef)
0387 #define BCM_6348_DDR_BASE       (0xdeadbeef)
0388 #define BCM_6348_ATM_BASE       (0xfffe4000)
0389 #define BCM_6348_XTM_BASE       (0xdeadbeef)
0390 #define BCM_6348_XTMDMA_BASE        (0xdeadbeef)
0391 #define BCM_6348_XTMDMAC_BASE       (0xdeadbeef)
0392 #define BCM_6348_XTMDMAS_BASE       (0xdeadbeef)
0393 #define BCM_6348_PCM_BASE       (0xdeadbeef)
0394 #define BCM_6348_PCMDMA_BASE        (0xdeadbeef)
0395 #define BCM_6348_PCMDMAC_BASE       (0xdeadbeef)
0396 #define BCM_6348_PCMDMAS_BASE       (0xdeadbeef)
0397 #define BCM_6348_RNG_BASE       (0xdeadbeef)
0398 #define BCM_6348_MISC_BASE      (0xdeadbeef)
0399 
0400 /*
0401  * 6358 register sets base address
0402  */
0403 #define BCM_6358_DSL_LMEM_BASE      (0xfff00000)
0404 #define BCM_6358_PERF_BASE      (0xfffe0000)
0405 #define BCM_6358_TIMER_BASE     (0xfffe0040)
0406 #define BCM_6358_WDT_BASE       (0xfffe005c)
0407 #define BCM_6358_UART0_BASE     (0xfffe0100)
0408 #define BCM_6358_UART1_BASE     (0xfffe0120)
0409 #define BCM_6358_GPIO_BASE      (0xfffe0080)
0410 #define BCM_6358_SPI_BASE       (0xfffe0800)
0411 #define BCM_6358_HSSPI_BASE     (0xdeadbeef)
0412 #define BCM_6358_UDC0_BASE      (0xfffe0800)
0413 #define BCM_6358_USBDMA_BASE        (0xdeadbeef)
0414 #define BCM_6358_OHCI0_BASE     (0xfffe1400)
0415 #define BCM_6358_OHCI_PRIV_BASE     (0xdeadbeef)
0416 #define BCM_6358_USBH_PRIV_BASE     (0xfffe1500)
0417 #define BCM_6358_USBD_BASE      (0xdeadbeef)
0418 #define BCM_6358_MPI_BASE       (0xfffe1000)
0419 #define BCM_6358_PCMCIA_BASE        (0xfffe1054)
0420 #define BCM_6358_PCIE_BASE      (0xdeadbeef)
0421 #define BCM_6358_SDRAM_REGS_BASE    (0xfffe2300)
0422 #define BCM_6358_M2M_BASE       (0xdeadbeef)
0423 #define BCM_6358_DSL_BASE       (0xfffe3000)
0424 #define BCM_6358_ENET0_BASE     (0xfffe4000)
0425 #define BCM_6358_ENET1_BASE     (0xfffe4800)
0426 #define BCM_6358_ENETDMA_BASE       (0xfffe5000)
0427 #define BCM_6358_ENETDMAC_BASE      (0xfffe5100)
0428 #define BCM_6358_ENETDMAS_BASE      (0xfffe5200)
0429 #define BCM_6358_ENETSW_BASE        (0xdeadbeef)
0430 #define BCM_6358_EHCI0_BASE     (0xfffe1300)
0431 #define BCM_6358_SDRAM_BASE     (0xdeadbeef)
0432 #define BCM_6358_MEMC_BASE      (0xfffe1200)
0433 #define BCM_6358_DDR_BASE       (0xfffe12a0)
0434 #define BCM_6358_ATM_BASE       (0xfffe2000)
0435 #define BCM_6358_XTM_BASE       (0xdeadbeef)
0436 #define BCM_6358_XTMDMA_BASE        (0xdeadbeef)
0437 #define BCM_6358_XTMDMAC_BASE       (0xdeadbeef)
0438 #define BCM_6358_XTMDMAS_BASE       (0xdeadbeef)
0439 #define BCM_6358_PCM_BASE       (0xfffe1600)
0440 #define BCM_6358_PCMDMA_BASE        (0xfffe1800)
0441 #define BCM_6358_PCMDMAC_BASE       (0xfffe1900)
0442 #define BCM_6358_PCMDMAS_BASE       (0xfffe1a00)
0443 #define BCM_6358_RNG_BASE       (0xdeadbeef)
0444 #define BCM_6358_MISC_BASE      (0xdeadbeef)
0445 
0446 
0447 /*
0448  * 6362 register sets base address
0449  */
0450 #define BCM_6362_DSL_LMEM_BASE      (0xdeadbeef)
0451 #define BCM_6362_PERF_BASE      (0xb0000000)
0452 #define BCM_6362_TIMER_BASE     (0xb0000040)
0453 #define BCM_6362_WDT_BASE       (0xb000005c)
0454 #define BCM_6362_UART0_BASE             (0xb0000100)
0455 #define BCM_6362_UART1_BASE     (0xb0000120)
0456 #define BCM_6362_GPIO_BASE      (0xb0000080)
0457 #define BCM_6362_SPI_BASE       (0xb0000800)
0458 #define BCM_6362_HSSPI_BASE     (0xb0001000)
0459 #define BCM_6362_UDC0_BASE      (0xdeadbeef)
0460 #define BCM_6362_USBDMA_BASE        (0xb000c000)
0461 #define BCM_6362_OHCI0_BASE     (0xb0002600)
0462 #define BCM_6362_OHCI_PRIV_BASE     (0xdeadbeef)
0463 #define BCM_6362_USBH_PRIV_BASE     (0xb0002700)
0464 #define BCM_6362_USBD_BASE      (0xb0002400)
0465 #define BCM_6362_MPI_BASE       (0xdeadbeef)
0466 #define BCM_6362_PCMCIA_BASE        (0xdeadbeef)
0467 #define BCM_6362_PCIE_BASE      (0xb0e40000)
0468 #define BCM_6362_SDRAM_REGS_BASE    (0xdeadbeef)
0469 #define BCM_6362_DSL_BASE       (0xdeadbeef)
0470 #define BCM_6362_UBUS_BASE      (0xdeadbeef)
0471 #define BCM_6362_ENET0_BASE     (0xdeadbeef)
0472 #define BCM_6362_ENET1_BASE     (0xdeadbeef)
0473 #define BCM_6362_ENETDMA_BASE       (0xb000d800)
0474 #define BCM_6362_ENETDMAC_BASE      (0xb000da00)
0475 #define BCM_6362_ENETDMAS_BASE      (0xb000dc00)
0476 #define BCM_6362_ENETSW_BASE        (0xb0e00000)
0477 #define BCM_6362_EHCI0_BASE     (0xb0002500)
0478 #define BCM_6362_SDRAM_BASE     (0xdeadbeef)
0479 #define BCM_6362_MEMC_BASE      (0xdeadbeef)
0480 #define BCM_6362_DDR_BASE       (0xb0003000)
0481 #define BCM_6362_M2M_BASE       (0xdeadbeef)
0482 #define BCM_6362_ATM_BASE       (0xdeadbeef)
0483 #define BCM_6362_XTM_BASE       (0xb0007800)
0484 #define BCM_6362_XTMDMA_BASE        (0xb000b800)
0485 #define BCM_6362_XTMDMAC_BASE       (0xdeadbeef)
0486 #define BCM_6362_XTMDMAS_BASE       (0xdeadbeef)
0487 #define BCM_6362_PCM_BASE       (0xb000a800)
0488 #define BCM_6362_PCMDMA_BASE        (0xdeadbeef)
0489 #define BCM_6362_PCMDMAC_BASE       (0xdeadbeef)
0490 #define BCM_6362_PCMDMAS_BASE       (0xdeadbeef)
0491 #define BCM_6362_RNG_BASE       (0xdeadbeef)
0492 #define BCM_6362_MISC_BASE      (0xb0001800)
0493 
0494 #define BCM_6362_NAND_REG_BASE      (0xb0000200)
0495 #define BCM_6362_NAND_CACHE_BASE    (0xb0000600)
0496 #define BCM_6362_LED_BASE       (0xb0001900)
0497 #define BCM_6362_IPSEC_BASE     (0xb0002800)
0498 #define BCM_6362_IPSEC_DMA_BASE     (0xb000d000)
0499 #define BCM_6362_WLAN_CHIPCOMMON_BASE   (0xb0004000)
0500 #define BCM_6362_WLAN_D11_BASE      (0xb0005000)
0501 #define BCM_6362_WLAN_SHIM_BASE     (0xb0007000)
0502 
0503 /*
0504  * 6368 register sets base address
0505  */
0506 #define BCM_6368_DSL_LMEM_BASE      (0xdeadbeef)
0507 #define BCM_6368_PERF_BASE      (0xb0000000)
0508 #define BCM_6368_TIMER_BASE     (0xb0000040)
0509 #define BCM_6368_WDT_BASE       (0xb000005c)
0510 #define BCM_6368_UART0_BASE     (0xb0000100)
0511 #define BCM_6368_UART1_BASE     (0xb0000120)
0512 #define BCM_6368_GPIO_BASE      (0xb0000080)
0513 #define BCM_6368_SPI_BASE       (0xb0000800)
0514 #define BCM_6368_HSSPI_BASE     (0xdeadbeef)
0515 #define BCM_6368_UDC0_BASE      (0xdeadbeef)
0516 #define BCM_6368_USBDMA_BASE        (0xb0004800)
0517 #define BCM_6368_OHCI0_BASE     (0xb0001600)
0518 #define BCM_6368_OHCI_PRIV_BASE     (0xdeadbeef)
0519 #define BCM_6368_USBH_PRIV_BASE     (0xb0001700)
0520 #define BCM_6368_USBD_BASE      (0xb0001400)
0521 #define BCM_6368_MPI_BASE       (0xb0001000)
0522 #define BCM_6368_PCMCIA_BASE        (0xb0001054)
0523 #define BCM_6368_PCIE_BASE      (0xdeadbeef)
0524 #define BCM_6368_SDRAM_REGS_BASE    (0xdeadbeef)
0525 #define BCM_6368_M2M_BASE       (0xdeadbeef)
0526 #define BCM_6368_DSL_BASE       (0xdeadbeef)
0527 #define BCM_6368_ENET0_BASE     (0xdeadbeef)
0528 #define BCM_6368_ENET1_BASE     (0xdeadbeef)
0529 #define BCM_6368_ENETDMA_BASE       (0xb0006800)
0530 #define BCM_6368_ENETDMAC_BASE      (0xb0006a00)
0531 #define BCM_6368_ENETDMAS_BASE      (0xb0006c00)
0532 #define BCM_6368_ENETSW_BASE        (0xb0f00000)
0533 #define BCM_6368_EHCI0_BASE     (0xb0001500)
0534 #define BCM_6368_SDRAM_BASE     (0xdeadbeef)
0535 #define BCM_6368_MEMC_BASE      (0xb0001200)
0536 #define BCM_6368_DDR_BASE       (0xb0001280)
0537 #define BCM_6368_ATM_BASE       (0xdeadbeef)
0538 #define BCM_6368_XTM_BASE       (0xb0001800)
0539 #define BCM_6368_XTMDMA_BASE        (0xb0005000)
0540 #define BCM_6368_XTMDMAC_BASE       (0xb0005200)
0541 #define BCM_6368_XTMDMAS_BASE       (0xb0005400)
0542 #define BCM_6368_PCM_BASE       (0xb0004000)
0543 #define BCM_6368_PCMDMA_BASE        (0xb0005800)
0544 #define BCM_6368_PCMDMAC_BASE       (0xb0005a00)
0545 #define BCM_6368_PCMDMAS_BASE       (0xb0005c00)
0546 #define BCM_6368_RNG_BASE       (0xb0004180)
0547 #define BCM_6368_MISC_BASE      (0xdeadbeef)
0548 
0549 
0550 extern const unsigned long *bcm63xx_regs_base;
0551 
0552 #define __GEN_CPU_REGS_TABLE(__cpu)                 \
0553     [RSET_DSL_LMEM]     = BCM_## __cpu ##_DSL_LMEM_BASE,    \
0554     [RSET_PERF]     = BCM_## __cpu ##_PERF_BASE,        \
0555     [RSET_TIMER]        = BCM_## __cpu ##_TIMER_BASE,       \
0556     [RSET_WDT]      = BCM_## __cpu ##_WDT_BASE,     \
0557     [RSET_UART0]        = BCM_## __cpu ##_UART0_BASE,       \
0558     [RSET_UART1]        = BCM_## __cpu ##_UART1_BASE,       \
0559     [RSET_GPIO]     = BCM_## __cpu ##_GPIO_BASE,        \
0560     [RSET_SPI]      = BCM_## __cpu ##_SPI_BASE,     \
0561     [RSET_HSSPI]        = BCM_## __cpu ##_HSSPI_BASE,       \
0562     [RSET_UDC0]     = BCM_## __cpu ##_UDC0_BASE,        \
0563     [RSET_OHCI0]        = BCM_## __cpu ##_OHCI0_BASE,       \
0564     [RSET_OHCI_PRIV]    = BCM_## __cpu ##_OHCI_PRIV_BASE,   \
0565     [RSET_USBH_PRIV]    = BCM_## __cpu ##_USBH_PRIV_BASE,   \
0566     [RSET_USBD]     = BCM_## __cpu ##_USBD_BASE,        \
0567     [RSET_USBDMA]       = BCM_## __cpu ##_USBDMA_BASE,      \
0568     [RSET_MPI]      = BCM_## __cpu ##_MPI_BASE,     \
0569     [RSET_PCMCIA]       = BCM_## __cpu ##_PCMCIA_BASE,      \
0570     [RSET_PCIE]     = BCM_## __cpu ##_PCIE_BASE,        \
0571     [RSET_DSL]      = BCM_## __cpu ##_DSL_BASE,     \
0572     [RSET_ENET0]        = BCM_## __cpu ##_ENET0_BASE,       \
0573     [RSET_ENET1]        = BCM_## __cpu ##_ENET1_BASE,       \
0574     [RSET_ENETDMA]      = BCM_## __cpu ##_ENETDMA_BASE,     \
0575     [RSET_ENETDMAC]     = BCM_## __cpu ##_ENETDMAC_BASE,    \
0576     [RSET_ENETDMAS]     = BCM_## __cpu ##_ENETDMAS_BASE,    \
0577     [RSET_ENETSW]       = BCM_## __cpu ##_ENETSW_BASE,      \
0578     [RSET_EHCI0]        = BCM_## __cpu ##_EHCI0_BASE,       \
0579     [RSET_SDRAM]        = BCM_## __cpu ##_SDRAM_BASE,       \
0580     [RSET_MEMC]     = BCM_## __cpu ##_MEMC_BASE,        \
0581     [RSET_DDR]      = BCM_## __cpu ##_DDR_BASE,     \
0582     [RSET_M2M]      = BCM_## __cpu ##_M2M_BASE,     \
0583     [RSET_ATM]      = BCM_## __cpu ##_ATM_BASE,     \
0584     [RSET_XTM]      = BCM_## __cpu ##_XTM_BASE,     \
0585     [RSET_XTMDMA]       = BCM_## __cpu ##_XTMDMA_BASE,      \
0586     [RSET_XTMDMAC]      = BCM_## __cpu ##_XTMDMAC_BASE,     \
0587     [RSET_XTMDMAS]      = BCM_## __cpu ##_XTMDMAS_BASE,     \
0588     [RSET_PCM]      = BCM_## __cpu ##_PCM_BASE,     \
0589     [RSET_PCMDMA]       = BCM_## __cpu ##_PCMDMA_BASE,      \
0590     [RSET_PCMDMAC]      = BCM_## __cpu ##_PCMDMAC_BASE,     \
0591     [RSET_PCMDMAS]      = BCM_## __cpu ##_PCMDMAS_BASE,     \
0592     [RSET_RNG]      = BCM_## __cpu ##_RNG_BASE,     \
0593     [RSET_MISC]     = BCM_## __cpu ##_MISC_BASE,        \
0594 
0595 
0596 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
0597 {
0598     return bcm63xx_regs_base[set];
0599 }
0600 
0601 /*
0602  * IRQ number changes across CPU too
0603  */
0604 enum bcm63xx_irq {
0605     IRQ_TIMER = 0,
0606     IRQ_SPI,
0607     IRQ_UART0,
0608     IRQ_UART1,
0609     IRQ_DSL,
0610     IRQ_ENET0,
0611     IRQ_ENET1,
0612     IRQ_ENET_PHY,
0613     IRQ_HSSPI,
0614     IRQ_OHCI0,
0615     IRQ_EHCI0,
0616     IRQ_USBD,
0617     IRQ_USBD_RXDMA0,
0618     IRQ_USBD_TXDMA0,
0619     IRQ_USBD_RXDMA1,
0620     IRQ_USBD_TXDMA1,
0621     IRQ_USBD_RXDMA2,
0622     IRQ_USBD_TXDMA2,
0623     IRQ_ENET0_RXDMA,
0624     IRQ_ENET0_TXDMA,
0625     IRQ_ENET1_RXDMA,
0626     IRQ_ENET1_TXDMA,
0627     IRQ_PCI,
0628     IRQ_PCMCIA,
0629     IRQ_ATM,
0630     IRQ_ENETSW_RXDMA0,
0631     IRQ_ENETSW_RXDMA1,
0632     IRQ_ENETSW_RXDMA2,
0633     IRQ_ENETSW_RXDMA3,
0634     IRQ_ENETSW_TXDMA0,
0635     IRQ_ENETSW_TXDMA1,
0636     IRQ_ENETSW_TXDMA2,
0637     IRQ_ENETSW_TXDMA3,
0638     IRQ_XTM,
0639     IRQ_XTM_DMA0,
0640 };
0641 
0642 /*
0643  * 3368 irqs
0644  */
0645 #define BCM_3368_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0646 #define BCM_3368_SPI_IRQ        (IRQ_INTERNAL_BASE + 1)
0647 #define BCM_3368_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0648 #define BCM_3368_UART1_IRQ      (IRQ_INTERNAL_BASE + 3)
0649 #define BCM_3368_DSL_IRQ        0
0650 #define BCM_3368_UDC0_IRQ       0
0651 #define BCM_3368_OHCI0_IRQ      0
0652 #define BCM_3368_ENET0_IRQ      (IRQ_INTERNAL_BASE + 8)
0653 #define BCM_3368_ENET1_IRQ      (IRQ_INTERNAL_BASE + 6)
0654 #define BCM_3368_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 9)
0655 #define BCM_3368_ENET0_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 15)
0656 #define BCM_3368_ENET0_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 16)
0657 #define BCM_3368_HSSPI_IRQ      0
0658 #define BCM_3368_EHCI0_IRQ      0
0659 #define BCM_3368_USBD_IRQ       0
0660 #define BCM_3368_USBD_RXDMA0_IRQ    0
0661 #define BCM_3368_USBD_TXDMA0_IRQ    0
0662 #define BCM_3368_USBD_RXDMA1_IRQ    0
0663 #define BCM_3368_USBD_TXDMA1_IRQ    0
0664 #define BCM_3368_USBD_RXDMA2_IRQ    0
0665 #define BCM_3368_USBD_TXDMA2_IRQ    0
0666 #define BCM_3368_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
0667 #define BCM_3368_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
0668 #define BCM_3368_PCI_IRQ        (IRQ_INTERNAL_BASE + 31)
0669 #define BCM_3368_PCMCIA_IRQ     0
0670 #define BCM_3368_ATM_IRQ        0
0671 #define BCM_3368_ENETSW_RXDMA0_IRQ  0
0672 #define BCM_3368_ENETSW_RXDMA1_IRQ  0
0673 #define BCM_3368_ENETSW_RXDMA2_IRQ  0
0674 #define BCM_3368_ENETSW_RXDMA3_IRQ  0
0675 #define BCM_3368_ENETSW_TXDMA0_IRQ  0
0676 #define BCM_3368_ENETSW_TXDMA1_IRQ  0
0677 #define BCM_3368_ENETSW_TXDMA2_IRQ  0
0678 #define BCM_3368_ENETSW_TXDMA3_IRQ  0
0679 #define BCM_3368_XTM_IRQ        0
0680 #define BCM_3368_XTM_DMA0_IRQ       0
0681 
0682 #define BCM_3368_EXT_IRQ0       (IRQ_INTERNAL_BASE + 25)
0683 #define BCM_3368_EXT_IRQ1       (IRQ_INTERNAL_BASE + 26)
0684 #define BCM_3368_EXT_IRQ2       (IRQ_INTERNAL_BASE + 27)
0685 #define BCM_3368_EXT_IRQ3       (IRQ_INTERNAL_BASE + 28)
0686 
0687 
0688 /*
0689  * 6328 irqs
0690  */
0691 #define BCM_6328_HIGH_IRQ_BASE      (IRQ_INTERNAL_BASE + 32)
0692 
0693 #define BCM_6328_TIMER_IRQ      (IRQ_INTERNAL_BASE + 31)
0694 #define BCM_6328_SPI_IRQ        0
0695 #define BCM_6328_UART0_IRQ      (IRQ_INTERNAL_BASE + 28)
0696 #define BCM_6328_UART1_IRQ      (BCM_6328_HIGH_IRQ_BASE + 7)
0697 #define BCM_6328_DSL_IRQ        (IRQ_INTERNAL_BASE + 4)
0698 #define BCM_6328_UDC0_IRQ       0
0699 #define BCM_6328_ENET0_IRQ      0
0700 #define BCM_6328_ENET1_IRQ      0
0701 #define BCM_6328_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 12)
0702 #define BCM_6328_HSSPI_IRQ      (IRQ_INTERNAL_BASE + 29)
0703 #define BCM_6328_OHCI0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 9)
0704 #define BCM_6328_EHCI0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 10)
0705 #define BCM_6328_USBD_IRQ       (IRQ_INTERNAL_BASE + 4)
0706 #define BCM_6328_USBD_RXDMA0_IRQ    (IRQ_INTERNAL_BASE + 5)
0707 #define BCM_6328_USBD_TXDMA0_IRQ    (IRQ_INTERNAL_BASE + 6)
0708 #define BCM_6328_USBD_RXDMA1_IRQ    (IRQ_INTERNAL_BASE + 7)
0709 #define BCM_6328_USBD_TXDMA1_IRQ    (IRQ_INTERNAL_BASE + 8)
0710 #define BCM_6328_USBD_RXDMA2_IRQ    (IRQ_INTERNAL_BASE + 9)
0711 #define BCM_6328_USBD_TXDMA2_IRQ    (IRQ_INTERNAL_BASE + 10)
0712 #define BCM_6328_PCMCIA_IRQ     0
0713 #define BCM_6328_ENET0_RXDMA_IRQ    0
0714 #define BCM_6328_ENET0_TXDMA_IRQ    0
0715 #define BCM_6328_ENET1_RXDMA_IRQ    0
0716 #define BCM_6328_ENET1_TXDMA_IRQ    0
0717 #define BCM_6328_PCI_IRQ        (IRQ_INTERNAL_BASE + 23)
0718 #define BCM_6328_ATM_IRQ        0
0719 #define BCM_6328_ENETSW_RXDMA0_IRQ  (BCM_6328_HIGH_IRQ_BASE + 0)
0720 #define BCM_6328_ENETSW_RXDMA1_IRQ  (BCM_6328_HIGH_IRQ_BASE + 1)
0721 #define BCM_6328_ENETSW_RXDMA2_IRQ  (BCM_6328_HIGH_IRQ_BASE + 2)
0722 #define BCM_6328_ENETSW_RXDMA3_IRQ  (BCM_6328_HIGH_IRQ_BASE + 3)
0723 #define BCM_6328_ENETSW_TXDMA0_IRQ  0
0724 #define BCM_6328_ENETSW_TXDMA1_IRQ  0
0725 #define BCM_6328_ENETSW_TXDMA2_IRQ  0
0726 #define BCM_6328_ENETSW_TXDMA3_IRQ  0
0727 #define BCM_6328_XTM_IRQ        (BCM_6328_HIGH_IRQ_BASE + 31)
0728 #define BCM_6328_XTM_DMA0_IRQ       (BCM_6328_HIGH_IRQ_BASE + 11)
0729 
0730 #define BCM_6328_PCM_DMA0_IRQ       (IRQ_INTERNAL_BASE + 2)
0731 #define BCM_6328_PCM_DMA1_IRQ       (IRQ_INTERNAL_BASE + 3)
0732 #define BCM_6328_EXT_IRQ0       (IRQ_INTERNAL_BASE + 24)
0733 #define BCM_6328_EXT_IRQ1       (IRQ_INTERNAL_BASE + 25)
0734 #define BCM_6328_EXT_IRQ2       (IRQ_INTERNAL_BASE + 26)
0735 #define BCM_6328_EXT_IRQ3       (IRQ_INTERNAL_BASE + 27)
0736 
0737 /*
0738  * 6338 irqs
0739  */
0740 #define BCM_6338_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0741 #define BCM_6338_SPI_IRQ        (IRQ_INTERNAL_BASE + 1)
0742 #define BCM_6338_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0743 #define BCM_6338_UART1_IRQ      0
0744 #define BCM_6338_DSL_IRQ        (IRQ_INTERNAL_BASE + 5)
0745 #define BCM_6338_ENET0_IRQ      (IRQ_INTERNAL_BASE + 8)
0746 #define BCM_6338_ENET1_IRQ      0
0747 #define BCM_6338_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 9)
0748 #define BCM_6338_HSSPI_IRQ      0
0749 #define BCM_6338_OHCI0_IRQ      0
0750 #define BCM_6338_EHCI0_IRQ      0
0751 #define BCM_6338_USBD_IRQ       0
0752 #define BCM_6338_USBD_RXDMA0_IRQ    0
0753 #define BCM_6338_USBD_TXDMA0_IRQ    0
0754 #define BCM_6338_USBD_RXDMA1_IRQ    0
0755 #define BCM_6338_USBD_TXDMA1_IRQ    0
0756 #define BCM_6338_USBD_RXDMA2_IRQ    0
0757 #define BCM_6338_USBD_TXDMA2_IRQ    0
0758 #define BCM_6338_ENET0_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 15)
0759 #define BCM_6338_ENET0_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 16)
0760 #define BCM_6338_ENET1_RXDMA_IRQ    0
0761 #define BCM_6338_ENET1_TXDMA_IRQ    0
0762 #define BCM_6338_PCI_IRQ        0
0763 #define BCM_6338_PCMCIA_IRQ     0
0764 #define BCM_6338_ATM_IRQ        0
0765 #define BCM_6338_ENETSW_RXDMA0_IRQ  0
0766 #define BCM_6338_ENETSW_RXDMA1_IRQ  0
0767 #define BCM_6338_ENETSW_RXDMA2_IRQ  0
0768 #define BCM_6338_ENETSW_RXDMA3_IRQ  0
0769 #define BCM_6338_ENETSW_TXDMA0_IRQ  0
0770 #define BCM_6338_ENETSW_TXDMA1_IRQ  0
0771 #define BCM_6338_ENETSW_TXDMA2_IRQ  0
0772 #define BCM_6338_ENETSW_TXDMA3_IRQ  0
0773 #define BCM_6338_XTM_IRQ        0
0774 #define BCM_6338_XTM_DMA0_IRQ       0
0775 
0776 /*
0777  * 6345 irqs
0778  */
0779 #define BCM_6345_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0780 #define BCM_6345_SPI_IRQ        0
0781 #define BCM_6345_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0782 #define BCM_6345_UART1_IRQ      0
0783 #define BCM_6345_DSL_IRQ        (IRQ_INTERNAL_BASE + 3)
0784 #define BCM_6345_ENET0_IRQ      (IRQ_INTERNAL_BASE + 8)
0785 #define BCM_6345_ENET1_IRQ      0
0786 #define BCM_6345_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 12)
0787 #define BCM_6345_HSSPI_IRQ      0
0788 #define BCM_6345_OHCI0_IRQ      0
0789 #define BCM_6345_EHCI0_IRQ      0
0790 #define BCM_6345_USBD_IRQ       0
0791 #define BCM_6345_USBD_RXDMA0_IRQ    0
0792 #define BCM_6345_USBD_TXDMA0_IRQ    0
0793 #define BCM_6345_USBD_RXDMA1_IRQ    0
0794 #define BCM_6345_USBD_TXDMA1_IRQ    0
0795 #define BCM_6345_USBD_RXDMA2_IRQ    0
0796 #define BCM_6345_USBD_TXDMA2_IRQ    0
0797 #define BCM_6345_ENET0_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 1)
0798 #define BCM_6345_ENET0_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 2)
0799 #define BCM_6345_ENET1_RXDMA_IRQ    0
0800 #define BCM_6345_ENET1_TXDMA_IRQ    0
0801 #define BCM_6345_PCI_IRQ        0
0802 #define BCM_6345_PCMCIA_IRQ     0
0803 #define BCM_6345_ATM_IRQ        0
0804 #define BCM_6345_ENETSW_RXDMA0_IRQ  0
0805 #define BCM_6345_ENETSW_RXDMA1_IRQ  0
0806 #define BCM_6345_ENETSW_RXDMA2_IRQ  0
0807 #define BCM_6345_ENETSW_RXDMA3_IRQ  0
0808 #define BCM_6345_ENETSW_TXDMA0_IRQ  0
0809 #define BCM_6345_ENETSW_TXDMA1_IRQ  0
0810 #define BCM_6345_ENETSW_TXDMA2_IRQ  0
0811 #define BCM_6345_ENETSW_TXDMA3_IRQ  0
0812 #define BCM_6345_XTM_IRQ        0
0813 #define BCM_6345_XTM_DMA0_IRQ       0
0814 
0815 /*
0816  * 6348 irqs
0817  */
0818 #define BCM_6348_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0819 #define BCM_6348_SPI_IRQ        (IRQ_INTERNAL_BASE + 1)
0820 #define BCM_6348_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0821 #define BCM_6348_UART1_IRQ      0
0822 #define BCM_6348_DSL_IRQ        (IRQ_INTERNAL_BASE + 4)
0823 #define BCM_6348_ENET0_IRQ      (IRQ_INTERNAL_BASE + 8)
0824 #define BCM_6348_ENET1_IRQ      (IRQ_INTERNAL_BASE + 7)
0825 #define BCM_6348_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 9)
0826 #define BCM_6348_HSSPI_IRQ      0
0827 #define BCM_6348_OHCI0_IRQ      (IRQ_INTERNAL_BASE + 12)
0828 #define BCM_6348_EHCI0_IRQ      0
0829 #define BCM_6348_USBD_IRQ       0
0830 #define BCM_6348_USBD_RXDMA0_IRQ    0
0831 #define BCM_6348_USBD_TXDMA0_IRQ    0
0832 #define BCM_6348_USBD_RXDMA1_IRQ    0
0833 #define BCM_6348_USBD_TXDMA1_IRQ    0
0834 #define BCM_6348_USBD_RXDMA2_IRQ    0
0835 #define BCM_6348_USBD_TXDMA2_IRQ    0
0836 #define BCM_6348_ENET0_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 20)
0837 #define BCM_6348_ENET0_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 21)
0838 #define BCM_6348_ENET1_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 22)
0839 #define BCM_6348_ENET1_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 23)
0840 #define BCM_6348_PCI_IRQ        (IRQ_INTERNAL_BASE + 24)
0841 #define BCM_6348_PCMCIA_IRQ     (IRQ_INTERNAL_BASE + 24)
0842 #define BCM_6348_ATM_IRQ        (IRQ_INTERNAL_BASE + 5)
0843 #define BCM_6348_ENETSW_RXDMA0_IRQ  0
0844 #define BCM_6348_ENETSW_RXDMA1_IRQ  0
0845 #define BCM_6348_ENETSW_RXDMA2_IRQ  0
0846 #define BCM_6348_ENETSW_RXDMA3_IRQ  0
0847 #define BCM_6348_ENETSW_TXDMA0_IRQ  0
0848 #define BCM_6348_ENETSW_TXDMA1_IRQ  0
0849 #define BCM_6348_ENETSW_TXDMA2_IRQ  0
0850 #define BCM_6348_ENETSW_TXDMA3_IRQ  0
0851 #define BCM_6348_XTM_IRQ        0
0852 #define BCM_6348_XTM_DMA0_IRQ       0
0853 
0854 /*
0855  * 6358 irqs
0856  */
0857 #define BCM_6358_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0858 #define BCM_6358_SPI_IRQ        (IRQ_INTERNAL_BASE + 1)
0859 #define BCM_6358_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0860 #define BCM_6358_UART1_IRQ      (IRQ_INTERNAL_BASE + 3)
0861 #define BCM_6358_DSL_IRQ        (IRQ_INTERNAL_BASE + 29)
0862 #define BCM_6358_ENET0_IRQ      (IRQ_INTERNAL_BASE + 8)
0863 #define BCM_6358_ENET1_IRQ      (IRQ_INTERNAL_BASE + 6)
0864 #define BCM_6358_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 9)
0865 #define BCM_6358_HSSPI_IRQ      0
0866 #define BCM_6358_OHCI0_IRQ      (IRQ_INTERNAL_BASE + 5)
0867 #define BCM_6358_EHCI0_IRQ      (IRQ_INTERNAL_BASE + 10)
0868 #define BCM_6358_USBD_IRQ       0
0869 #define BCM_6358_USBD_RXDMA0_IRQ    0
0870 #define BCM_6358_USBD_TXDMA0_IRQ    0
0871 #define BCM_6358_USBD_RXDMA1_IRQ    0
0872 #define BCM_6358_USBD_TXDMA1_IRQ    0
0873 #define BCM_6358_USBD_RXDMA2_IRQ    0
0874 #define BCM_6358_USBD_TXDMA2_IRQ    0
0875 #define BCM_6358_ENET0_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 15)
0876 #define BCM_6358_ENET0_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 16)
0877 #define BCM_6358_ENET1_RXDMA_IRQ    (IRQ_INTERNAL_BASE + 17)
0878 #define BCM_6358_ENET1_TXDMA_IRQ    (IRQ_INTERNAL_BASE + 18)
0879 #define BCM_6358_PCI_IRQ        (IRQ_INTERNAL_BASE + 31)
0880 #define BCM_6358_PCMCIA_IRQ     (IRQ_INTERNAL_BASE + 24)
0881 #define BCM_6358_ATM_IRQ        (IRQ_INTERNAL_BASE + 19)
0882 #define BCM_6358_ENETSW_RXDMA0_IRQ  0
0883 #define BCM_6358_ENETSW_RXDMA1_IRQ  0
0884 #define BCM_6358_ENETSW_RXDMA2_IRQ  0
0885 #define BCM_6358_ENETSW_RXDMA3_IRQ  0
0886 #define BCM_6358_ENETSW_TXDMA0_IRQ  0
0887 #define BCM_6358_ENETSW_TXDMA1_IRQ  0
0888 #define BCM_6358_ENETSW_TXDMA2_IRQ  0
0889 #define BCM_6358_ENETSW_TXDMA3_IRQ  0
0890 #define BCM_6358_XTM_IRQ        0
0891 #define BCM_6358_XTM_DMA0_IRQ       0
0892 
0893 #define BCM_6358_PCM_DMA0_IRQ       (IRQ_INTERNAL_BASE + 23)
0894 #define BCM_6358_PCM_DMA1_IRQ       (IRQ_INTERNAL_BASE + 24)
0895 #define BCM_6358_EXT_IRQ0       (IRQ_INTERNAL_BASE + 25)
0896 #define BCM_6358_EXT_IRQ1       (IRQ_INTERNAL_BASE + 26)
0897 #define BCM_6358_EXT_IRQ2       (IRQ_INTERNAL_BASE + 27)
0898 #define BCM_6358_EXT_IRQ3       (IRQ_INTERNAL_BASE + 28)
0899 
0900 /*
0901  * 6362 irqs
0902  */
0903 #define BCM_6362_HIGH_IRQ_BASE      (IRQ_INTERNAL_BASE + 32)
0904 
0905 #define BCM_6362_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0906 #define BCM_6362_SPI_IRQ        (IRQ_INTERNAL_BASE + 2)
0907 #define BCM_6362_UART0_IRQ      (IRQ_INTERNAL_BASE + 3)
0908 #define BCM_6362_UART1_IRQ      (IRQ_INTERNAL_BASE + 4)
0909 #define BCM_6362_DSL_IRQ        (IRQ_INTERNAL_BASE + 28)
0910 #define BCM_6362_UDC0_IRQ       0
0911 #define BCM_6362_ENET0_IRQ      0
0912 #define BCM_6362_ENET1_IRQ      0
0913 #define BCM_6362_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 14)
0914 #define BCM_6362_HSSPI_IRQ      (IRQ_INTERNAL_BASE + 5)
0915 #define BCM_6362_OHCI0_IRQ      (IRQ_INTERNAL_BASE + 9)
0916 #define BCM_6362_EHCI0_IRQ      (IRQ_INTERNAL_BASE + 10)
0917 #define BCM_6362_USBD_IRQ       (IRQ_INTERNAL_BASE + 11)
0918 #define BCM_6362_USBD_RXDMA0_IRQ    (IRQ_INTERNAL_BASE + 20)
0919 #define BCM_6362_USBD_TXDMA0_IRQ    (IRQ_INTERNAL_BASE + 21)
0920 #define BCM_6362_USBD_RXDMA1_IRQ    (IRQ_INTERNAL_BASE + 22)
0921 #define BCM_6362_USBD_TXDMA1_IRQ    (IRQ_INTERNAL_BASE + 23)
0922 #define BCM_6362_USBD_RXDMA2_IRQ    (IRQ_INTERNAL_BASE + 24)
0923 #define BCM_6362_USBD_TXDMA2_IRQ    (IRQ_INTERNAL_BASE + 25)
0924 #define BCM_6362_PCMCIA_IRQ     0
0925 #define BCM_6362_ENET0_RXDMA_IRQ    0
0926 #define BCM_6362_ENET0_TXDMA_IRQ    0
0927 #define BCM_6362_ENET1_RXDMA_IRQ    0
0928 #define BCM_6362_ENET1_TXDMA_IRQ    0
0929 #define BCM_6362_PCI_IRQ        (IRQ_INTERNAL_BASE + 30)
0930 #define BCM_6362_ATM_IRQ        0
0931 #define BCM_6362_ENETSW_RXDMA0_IRQ  (BCM_6362_HIGH_IRQ_BASE + 0)
0932 #define BCM_6362_ENETSW_RXDMA1_IRQ  (BCM_6362_HIGH_IRQ_BASE + 1)
0933 #define BCM_6362_ENETSW_RXDMA2_IRQ  (BCM_6362_HIGH_IRQ_BASE + 2)
0934 #define BCM_6362_ENETSW_RXDMA3_IRQ  (BCM_6362_HIGH_IRQ_BASE + 3)
0935 #define BCM_6362_ENETSW_TXDMA0_IRQ  0
0936 #define BCM_6362_ENETSW_TXDMA1_IRQ  0
0937 #define BCM_6362_ENETSW_TXDMA2_IRQ  0
0938 #define BCM_6362_ENETSW_TXDMA3_IRQ  0
0939 #define BCM_6362_XTM_IRQ        0
0940 #define BCM_6362_XTM_DMA0_IRQ       (BCM_6362_HIGH_IRQ_BASE + 12)
0941 
0942 #define BCM_6362_RING_OSC_IRQ       (IRQ_INTERNAL_BASE + 1)
0943 #define BCM_6362_WLAN_GPIO_IRQ      (IRQ_INTERNAL_BASE + 6)
0944 #define BCM_6362_WLAN_IRQ       (IRQ_INTERNAL_BASE + 7)
0945 #define BCM_6362_IPSEC_IRQ      (IRQ_INTERNAL_BASE + 8)
0946 #define BCM_6362_NAND_IRQ       (IRQ_INTERNAL_BASE + 12)
0947 #define BCM_6362_PCM_IRQ        (IRQ_INTERNAL_BASE + 13)
0948 #define BCM_6362_DG_IRQ         (IRQ_INTERNAL_BASE + 15)
0949 #define BCM_6362_EPHY_ENERGY0_IRQ   (IRQ_INTERNAL_BASE + 16)
0950 #define BCM_6362_EPHY_ENERGY1_IRQ   (IRQ_INTERNAL_BASE + 17)
0951 #define BCM_6362_EPHY_ENERGY2_IRQ   (IRQ_INTERNAL_BASE + 18)
0952 #define BCM_6362_EPHY_ENERGY3_IRQ   (IRQ_INTERNAL_BASE + 19)
0953 #define BCM_6362_IPSEC_DMA0_IRQ     (IRQ_INTERNAL_BASE + 26)
0954 #define BCM_6362_IPSEC_DMA1_IRQ     (IRQ_INTERNAL_BASE + 27)
0955 #define BCM_6362_FAP0_IRQ       (IRQ_INTERNAL_BASE + 29)
0956 #define BCM_6362_PCM_DMA0_IRQ       (BCM_6362_HIGH_IRQ_BASE + 4)
0957 #define BCM_6362_PCM_DMA1_IRQ       (BCM_6362_HIGH_IRQ_BASE + 5)
0958 #define BCM_6362_DECT0_IRQ      (BCM_6362_HIGH_IRQ_BASE + 6)
0959 #define BCM_6362_DECT1_IRQ      (BCM_6362_HIGH_IRQ_BASE + 7)
0960 #define BCM_6362_EXT_IRQ0       (BCM_6362_HIGH_IRQ_BASE + 8)
0961 #define BCM_6362_EXT_IRQ1       (BCM_6362_HIGH_IRQ_BASE + 9)
0962 #define BCM_6362_EXT_IRQ2       (BCM_6362_HIGH_IRQ_BASE + 10)
0963 #define BCM_6362_EXT_IRQ3       (BCM_6362_HIGH_IRQ_BASE + 11)
0964 
0965 /*
0966  * 6368 irqs
0967  */
0968 #define BCM_6368_HIGH_IRQ_BASE      (IRQ_INTERNAL_BASE + 32)
0969 
0970 #define BCM_6368_TIMER_IRQ      (IRQ_INTERNAL_BASE + 0)
0971 #define BCM_6368_SPI_IRQ        (IRQ_INTERNAL_BASE + 1)
0972 #define BCM_6368_UART0_IRQ      (IRQ_INTERNAL_BASE + 2)
0973 #define BCM_6368_UART1_IRQ      (IRQ_INTERNAL_BASE + 3)
0974 #define BCM_6368_DSL_IRQ        (IRQ_INTERNAL_BASE + 4)
0975 #define BCM_6368_ENET0_IRQ      0
0976 #define BCM_6368_ENET1_IRQ      0
0977 #define BCM_6368_ENET_PHY_IRQ       (IRQ_INTERNAL_BASE + 15)
0978 #define BCM_6368_HSSPI_IRQ      0
0979 #define BCM_6368_OHCI0_IRQ      (IRQ_INTERNAL_BASE + 5)
0980 #define BCM_6368_EHCI0_IRQ      (IRQ_INTERNAL_BASE + 7)
0981 #define BCM_6368_USBD_IRQ       (IRQ_INTERNAL_BASE + 8)
0982 #define BCM_6368_USBD_RXDMA0_IRQ    (IRQ_INTERNAL_BASE + 26)
0983 #define BCM_6368_USBD_TXDMA0_IRQ    (IRQ_INTERNAL_BASE + 27)
0984 #define BCM_6368_USBD_RXDMA1_IRQ    (IRQ_INTERNAL_BASE + 28)
0985 #define BCM_6368_USBD_TXDMA1_IRQ    (IRQ_INTERNAL_BASE + 29)
0986 #define BCM_6368_USBD_RXDMA2_IRQ    (IRQ_INTERNAL_BASE + 30)
0987 #define BCM_6368_USBD_TXDMA2_IRQ    (IRQ_INTERNAL_BASE + 31)
0988 #define BCM_6368_PCMCIA_IRQ     0
0989 #define BCM_6368_ENET0_RXDMA_IRQ    0
0990 #define BCM_6368_ENET0_TXDMA_IRQ    0
0991 #define BCM_6368_ENET1_RXDMA_IRQ    0
0992 #define BCM_6368_ENET1_TXDMA_IRQ    0
0993 #define BCM_6368_PCI_IRQ        (IRQ_INTERNAL_BASE + 13)
0994 #define BCM_6368_ATM_IRQ        0
0995 #define BCM_6368_ENETSW_RXDMA0_IRQ  (BCM_6368_HIGH_IRQ_BASE + 0)
0996 #define BCM_6368_ENETSW_RXDMA1_IRQ  (BCM_6368_HIGH_IRQ_BASE + 1)
0997 #define BCM_6368_ENETSW_RXDMA2_IRQ  (BCM_6368_HIGH_IRQ_BASE + 2)
0998 #define BCM_6368_ENETSW_RXDMA3_IRQ  (BCM_6368_HIGH_IRQ_BASE + 3)
0999 #define BCM_6368_ENETSW_TXDMA0_IRQ  (BCM_6368_HIGH_IRQ_BASE + 4)
1000 #define BCM_6368_ENETSW_TXDMA1_IRQ  (BCM_6368_HIGH_IRQ_BASE + 5)
1001 #define BCM_6368_ENETSW_TXDMA2_IRQ  (BCM_6368_HIGH_IRQ_BASE + 6)
1002 #define BCM_6368_ENETSW_TXDMA3_IRQ  (BCM_6368_HIGH_IRQ_BASE + 7)
1003 #define BCM_6368_XTM_IRQ        (IRQ_INTERNAL_BASE + 11)
1004 #define BCM_6368_XTM_DMA0_IRQ       (BCM_6368_HIGH_IRQ_BASE + 8)
1005 
1006 #define BCM_6368_PCM_DMA0_IRQ       (BCM_6368_HIGH_IRQ_BASE + 30)
1007 #define BCM_6368_PCM_DMA1_IRQ       (BCM_6368_HIGH_IRQ_BASE + 31)
1008 #define BCM_6368_EXT_IRQ0       (IRQ_INTERNAL_BASE + 20)
1009 #define BCM_6368_EXT_IRQ1       (IRQ_INTERNAL_BASE + 21)
1010 #define BCM_6368_EXT_IRQ2       (IRQ_INTERNAL_BASE + 22)
1011 #define BCM_6368_EXT_IRQ3       (IRQ_INTERNAL_BASE + 23)
1012 #define BCM_6368_EXT_IRQ4       (IRQ_INTERNAL_BASE + 24)
1013 #define BCM_6368_EXT_IRQ5       (IRQ_INTERNAL_BASE + 25)
1014 
1015 extern const int *bcm63xx_irqs;
1016 
1017 #define __GEN_CPU_IRQ_TABLE(__cpu)                  \
1018     [IRQ_TIMER]     = BCM_## __cpu ##_TIMER_IRQ,        \
1019     [IRQ_SPI]       = BCM_## __cpu ##_SPI_IRQ,      \
1020     [IRQ_UART0]     = BCM_## __cpu ##_UART0_IRQ,        \
1021     [IRQ_UART1]     = BCM_## __cpu ##_UART1_IRQ,        \
1022     [IRQ_DSL]       = BCM_## __cpu ##_DSL_IRQ,      \
1023     [IRQ_ENET0]     = BCM_## __cpu ##_ENET0_IRQ,        \
1024     [IRQ_ENET1]     = BCM_## __cpu ##_ENET1_IRQ,        \
1025     [IRQ_ENET_PHY]      = BCM_## __cpu ##_ENET_PHY_IRQ,     \
1026     [IRQ_HSSPI]     = BCM_## __cpu ##_HSSPI_IRQ,        \
1027     [IRQ_OHCI0]     = BCM_## __cpu ##_OHCI0_IRQ,        \
1028     [IRQ_EHCI0]     = BCM_## __cpu ##_EHCI0_IRQ,        \
1029     [IRQ_USBD]      = BCM_## __cpu ##_USBD_IRQ,     \
1030     [IRQ_USBD_RXDMA0]   = BCM_## __cpu ##_USBD_RXDMA0_IRQ,  \
1031     [IRQ_USBD_TXDMA0]   = BCM_## __cpu ##_USBD_TXDMA0_IRQ,  \
1032     [IRQ_USBD_RXDMA1]   = BCM_## __cpu ##_USBD_RXDMA1_IRQ,  \
1033     [IRQ_USBD_TXDMA1]   = BCM_## __cpu ##_USBD_TXDMA1_IRQ,  \
1034     [IRQ_USBD_RXDMA2]   = BCM_## __cpu ##_USBD_RXDMA2_IRQ,  \
1035     [IRQ_USBD_TXDMA2]   = BCM_## __cpu ##_USBD_TXDMA2_IRQ,  \
1036     [IRQ_ENET0_RXDMA]   = BCM_## __cpu ##_ENET0_RXDMA_IRQ,  \
1037     [IRQ_ENET0_TXDMA]   = BCM_## __cpu ##_ENET0_TXDMA_IRQ,  \
1038     [IRQ_ENET1_RXDMA]   = BCM_## __cpu ##_ENET1_RXDMA_IRQ,  \
1039     [IRQ_ENET1_TXDMA]   = BCM_## __cpu ##_ENET1_TXDMA_IRQ,  \
1040     [IRQ_PCI]       = BCM_## __cpu ##_PCI_IRQ,      \
1041     [IRQ_PCMCIA]        = BCM_## __cpu ##_PCMCIA_IRQ,       \
1042     [IRQ_ATM]       = BCM_## __cpu ##_ATM_IRQ,      \
1043     [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,    \
1044     [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,    \
1045     [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,    \
1046     [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,    \
1047     [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,    \
1048     [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,    \
1049     [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,    \
1050     [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,    \
1051     [IRQ_XTM]       = BCM_## __cpu ##_XTM_IRQ,      \
1052     [IRQ_XTM_DMA0]      = BCM_## __cpu ##_XTM_DMA0_IRQ,     \
1053 
1054 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
1055 {
1056     return bcm63xx_irqs[irq];
1057 }
1058 
1059 /*
1060  * return installed memory size
1061  */
1062 unsigned int bcm63xx_get_memory_size(void);
1063 
1064 void bcm63xx_machine_halt(void);
1065 
1066 void bcm63xx_machine_reboot(void);
1067 
1068 #endif /* !BCM63XX_CPU_H_ */
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