asm/mach-au1x00/gpio-au1300.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
0004  *
0005  * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
0006  */
0007
0008 #ifndef _GPIO_AU1300_H_
0009 #define _GPIO_AU1300_H_
0010
0011 #include <asm/addrspace.h>
0012 #include <asm/io.h>
0013 #include <asm/mach-au1x00/au1000.h>
0014
0015 struct gpio;
0016 struct gpio_chip;
0017
0018 /* with the current GPIC design, up to 128 GPIOs are possible.
0019  * The only implementation so far is in the Au1300, which has 75 externally
0020  * available GPIOs.
0021  */
0022 #define AU1300_GPIO_BASE    0
0023 #define AU1300_GPIO_NUM     75
0024 #define AU1300_GPIO_MAX     (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
0025
0026 #define AU1300_GPIC_ADDR    \
0027     (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
0028
0029 static inline int au1300_gpio_get_value(unsigned int gpio)
0030 {
0031     void __iomem *roff = AU1300_GPIC_ADDR;
0032     int bit;
0033
0034     gpio -= AU1300_GPIO_BASE;
0035     roff += GPIC_GPIO_BANKOFF(gpio);
0036     bit = GPIC_GPIO_TO_BIT(gpio);
0037     return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
0038 }
0039
0040 static inline int au1300_gpio_direction_input(unsigned int gpio)
0041 {
0042     void __iomem *roff = AU1300_GPIC_ADDR;
0043     unsigned long bit;
0044
0045     gpio -= AU1300_GPIO_BASE;
0046
0047     roff += GPIC_GPIO_BANKOFF(gpio);
0048     bit = GPIC_GPIO_TO_BIT(gpio);
0049     __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
0050     wmb();
0051
0052     return 0;
0053 }
0054
0055 static inline int au1300_gpio_set_value(unsigned int gpio, int v)
0056 {
0057     void __iomem *roff = AU1300_GPIC_ADDR;
0058     unsigned long bit;
0059
0060     gpio -= AU1300_GPIO_BASE;
0061
0062     roff += GPIC_GPIO_BANKOFF(gpio);
0063     bit = GPIC_GPIO_TO_BIT(gpio);
0064     __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
0065                     : AU1300_GPIC_PINVALCLR));
0066     wmb();
0067
0068     return 0;
0069 }
0070
0071 static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
0072 {
0073     /* hw switches to output automatically */
0074     return au1300_gpio_set_value(gpio, v);
0075 }
0076
0077 static inline int au1300_gpio_to_irq(unsigned int gpio)
0078 {
0079     return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
0080 }
0081
0082 static inline int au1300_irq_to_gpio(unsigned int irq)
0083 {
0084     return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
0085 }
0086
0087 static inline int au1300_gpio_is_valid(unsigned int gpio)
0088 {
0089     int ret;
0090
0091     switch (alchemy_get_cputype()) {
0092     case ALCHEMY_CPU_AU1300:
0093         ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
0094         break;
0095     default:
0096         ret = 0;
0097     }
0098     return ret;
0099 }
0100
0101 static inline int au1300_gpio_cansleep(unsigned int gpio)
0102 {
0103     return 0;
0104 }
0105
0106 /* hardware remembers gpio 0-63 levels on powerup */
0107 static inline int au1300_gpio_getinitlvl(unsigned int gpio)
0108 {
0109     void __iomem *roff = AU1300_GPIC_ADDR;
0110     unsigned long v;
0111
0112     if (unlikely(gpio > 63))
0113         return 0;
0114     else if (gpio > 31) {
0115         gpio -= 32;
0116         roff += 4;
0117     }
0118
0119     v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
0120     return (v >> gpio) & 1;
0121 }
0122
0123 #endif /* _GPIO_AU1300_H_ */