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0001 /*
0002  * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
0003  *
0004  * Copyright (c) 2009 Manuel Lauss.
0005  *
0006  * Licensed under the terms outlined in the file COPYING.
0007  */
0008 
0009 #ifndef _ALCHEMY_GPIO_AU1000_H_
0010 #define _ALCHEMY_GPIO_AU1000_H_
0011 
0012 #include <asm/mach-au1x00/au1000.h>
0013 
0014 /* The default GPIO numberspace as documented in the Alchemy manuals.
0015  * GPIO0-31 from GPIO1 block,   GPIO200-215 from GPIO2 block.
0016  */
0017 #define ALCHEMY_GPIO1_BASE  0
0018 #define ALCHEMY_GPIO2_BASE  200
0019 
0020 #define ALCHEMY_GPIO1_NUM   32
0021 #define ALCHEMY_GPIO2_NUM   16
0022 #define ALCHEMY_GPIO1_MAX   (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
0023 #define ALCHEMY_GPIO2_MAX   (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
0024 
0025 #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
0026 
0027 /* GPIO1 registers within SYS_ area */
0028 #define AU1000_SYS_TRIOUTRD 0x100
0029 #define AU1000_SYS_TRIOUTCLR    0x100
0030 #define AU1000_SYS_OUTPUTRD 0x108
0031 #define AU1000_SYS_OUTPUTSET    0x108
0032 #define AU1000_SYS_OUTPUTCLR    0x10C
0033 #define AU1000_SYS_PINSTATERD   0x110
0034 #define AU1000_SYS_PININPUTEN   0x110
0035 
0036 /* register offsets within GPIO2 block */
0037 #define AU1000_GPIO2_DIR    0x00
0038 #define AU1000_GPIO2_OUTPUT 0x08
0039 #define AU1000_GPIO2_PINSTATE   0x0C
0040 #define AU1000_GPIO2_INTENABLE  0x10
0041 #define AU1000_GPIO2_ENABLE 0x14
0042 
0043 struct gpio;
0044 
0045 static inline int au1000_gpio1_to_irq(int gpio)
0046 {
0047     return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
0048 }
0049 
0050 static inline int au1000_gpio2_to_irq(int gpio)
0051 {
0052     return -ENXIO;
0053 }
0054 
0055 static inline int au1000_irq_to_gpio(int irq)
0056 {
0057     if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
0058         return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
0059 
0060     return -ENXIO;
0061 }
0062 
0063 static inline int au1500_gpio1_to_irq(int gpio)
0064 {
0065     gpio -= ALCHEMY_GPIO1_BASE;
0066 
0067     switch (gpio) {
0068     case 0 ... 15:
0069     case 20:
0070     case 23 ... 28: return MAKE_IRQ(1, gpio);
0071     }
0072 
0073     return -ENXIO;
0074 }
0075 
0076 static inline int au1500_gpio2_to_irq(int gpio)
0077 {
0078     gpio -= ALCHEMY_GPIO2_BASE;
0079 
0080     switch (gpio) {
0081     case 0 ... 3:   return MAKE_IRQ(1, 16 + gpio - 0);
0082     case 4 ... 5:   return MAKE_IRQ(1, 21 + gpio - 4);
0083     case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
0084     }
0085 
0086     return -ENXIO;
0087 }
0088 
0089 static inline int au1500_irq_to_gpio(int irq)
0090 {
0091     switch (irq) {
0092     case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
0093     case AU1500_GPIO20_INT:
0094     case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
0095         return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
0096     case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
0097         return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
0098     case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
0099         return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
0100     case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
0101         return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
0102     case AU1500_GPIO208_215_INT:
0103         return ALCHEMY_GPIO2_BASE + 8;
0104     }
0105 
0106     return -ENXIO;
0107 }
0108 
0109 static inline int au1100_gpio1_to_irq(int gpio)
0110 {
0111     return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
0112 }
0113 
0114 static inline int au1100_gpio2_to_irq(int gpio)
0115 {
0116     gpio -= ALCHEMY_GPIO2_BASE;
0117 
0118     if ((gpio >= 8) && (gpio <= 15))
0119         return MAKE_IRQ(0, 29);     /* shared GPIO208_215 */
0120 
0121     return -ENXIO;
0122 }
0123 
0124 static inline int au1100_irq_to_gpio(int irq)
0125 {
0126     switch (irq) {
0127     case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
0128         return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
0129     case AU1100_GPIO208_215_INT:
0130         return ALCHEMY_GPIO2_BASE + 8;
0131     }
0132 
0133     return -ENXIO;
0134 }
0135 
0136 static inline int au1550_gpio1_to_irq(int gpio)
0137 {
0138     gpio -= ALCHEMY_GPIO1_BASE;
0139 
0140     switch (gpio) {
0141     case 0 ... 15:
0142     case 20 ... 28: return MAKE_IRQ(1, gpio);
0143     case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
0144     }
0145 
0146     return -ENXIO;
0147 }
0148 
0149 static inline int au1550_gpio2_to_irq(int gpio)
0150 {
0151     gpio -= ALCHEMY_GPIO2_BASE;
0152 
0153     switch (gpio) {
0154     case 0:     return MAKE_IRQ(1, 16);
0155     case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
0156     case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
0157     case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
0158     }
0159 
0160     return -ENXIO;
0161 }
0162 
0163 static inline int au1550_irq_to_gpio(int irq)
0164 {
0165     switch (irq) {
0166     case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
0167         return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
0168     case AU1550_GPIO200_INT:
0169     case AU1550_GPIO201_205_INT:
0170         return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
0171     case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
0172         return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
0173     case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
0174         return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
0175     }
0176 
0177     return -ENXIO;
0178 }
0179 
0180 static inline int au1200_gpio1_to_irq(int gpio)
0181 {
0182     return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
0183 }
0184 
0185 static inline int au1200_gpio2_to_irq(int gpio)
0186 {
0187     gpio -= ALCHEMY_GPIO2_BASE;
0188 
0189     switch (gpio) {
0190     case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
0191     case 3:     return MAKE_IRQ(0, 22);
0192     case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);
0193     case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
0194     }
0195 
0196     return -ENXIO;
0197 }
0198 
0199 static inline int au1200_irq_to_gpio(int irq)
0200 {
0201     switch (irq) {
0202     case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
0203         return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
0204     case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
0205         return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
0206     case AU1200_GPIO203_INT:
0207         return ALCHEMY_GPIO2_BASE + 3;
0208     case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
0209         return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
0210     }
0211 
0212     return -ENXIO;
0213 }
0214 
0215 /*
0216  * GPIO1 block macros for common linux gpio functions.
0217  */
0218 static inline void alchemy_gpio1_set_value(int gpio, int v)
0219 {
0220     unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
0221     unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
0222     alchemy_wrsys(mask, r);
0223 }
0224 
0225 static inline int alchemy_gpio1_get_value(int gpio)
0226 {
0227     unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
0228     return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
0229 }
0230 
0231 static inline int alchemy_gpio1_direction_input(int gpio)
0232 {
0233     unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
0234     alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
0235     return 0;
0236 }
0237 
0238 static inline int alchemy_gpio1_direction_output(int gpio, int v)
0239 {
0240     /* hardware switches to "output" mode when one of the two
0241      * "set_value" registers is accessed.
0242      */
0243     alchemy_gpio1_set_value(gpio, v);
0244     return 0;
0245 }
0246 
0247 static inline int alchemy_gpio1_is_valid(int gpio)
0248 {
0249     return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
0250 }
0251 
0252 static inline int alchemy_gpio1_to_irq(int gpio)
0253 {
0254     switch (alchemy_get_cputype()) {
0255     case ALCHEMY_CPU_AU1000:
0256         return au1000_gpio1_to_irq(gpio);
0257     case ALCHEMY_CPU_AU1100:
0258         return au1100_gpio1_to_irq(gpio);
0259     case ALCHEMY_CPU_AU1500:
0260         return au1500_gpio1_to_irq(gpio);
0261     case ALCHEMY_CPU_AU1550:
0262         return au1550_gpio1_to_irq(gpio);
0263     case ALCHEMY_CPU_AU1200:
0264         return au1200_gpio1_to_irq(gpio);
0265     }
0266     return -ENXIO;
0267 }
0268 
0269 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
0270  * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200/Au1300 this
0271  * register enables use of GPIOs as wake source.
0272  */
0273 static inline void alchemy_gpio1_input_enable(void)
0274 {
0275     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
0276     __raw_writel(0, base + 0x110);      /* the write op is key */
0277     wmb();
0278 }
0279 
0280 /*
0281  * GPIO2 block macros for common linux GPIO functions. The 'gpio'
0282  * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
0283  */
0284 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
0285 {
0286     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0287     unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
0288     unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
0289 
0290     if (to_out)
0291         d |= mask;
0292     else
0293         d &= ~mask;
0294     __raw_writel(d, base + AU1000_GPIO2_DIR);
0295     wmb();
0296 }
0297 
0298 static inline void alchemy_gpio2_set_value(int gpio, int v)
0299 {
0300     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0301     unsigned long mask;
0302     mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
0303     __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
0304     wmb();
0305 }
0306 
0307 static inline int alchemy_gpio2_get_value(int gpio)
0308 {
0309     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0310     return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
0311                 (1 << (gpio - ALCHEMY_GPIO2_BASE));
0312 }
0313 
0314 static inline int alchemy_gpio2_direction_input(int gpio)
0315 {
0316     unsigned long flags;
0317     local_irq_save(flags);
0318     __alchemy_gpio2_mod_dir(gpio, 0);
0319     local_irq_restore(flags);
0320     return 0;
0321 }
0322 
0323 static inline int alchemy_gpio2_direction_output(int gpio, int v)
0324 {
0325     unsigned long flags;
0326     alchemy_gpio2_set_value(gpio, v);
0327     local_irq_save(flags);
0328     __alchemy_gpio2_mod_dir(gpio, 1);
0329     local_irq_restore(flags);
0330     return 0;
0331 }
0332 
0333 static inline int alchemy_gpio2_is_valid(int gpio)
0334 {
0335     return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
0336 }
0337 
0338 static inline int alchemy_gpio2_to_irq(int gpio)
0339 {
0340     switch (alchemy_get_cputype()) {
0341     case ALCHEMY_CPU_AU1000:
0342         return au1000_gpio2_to_irq(gpio);
0343     case ALCHEMY_CPU_AU1100:
0344         return au1100_gpio2_to_irq(gpio);
0345     case ALCHEMY_CPU_AU1500:
0346         return au1500_gpio2_to_irq(gpio);
0347     case ALCHEMY_CPU_AU1550:
0348         return au1550_gpio2_to_irq(gpio);
0349     case ALCHEMY_CPU_AU1200:
0350         return au1200_gpio2_to_irq(gpio);
0351     }
0352     return -ENXIO;
0353 }
0354 
0355 /**********************************************************************/
0356 
0357 /* GPIO2 shared interrupts and control */
0358 
0359 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
0360 {
0361     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0362     unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
0363     if (en)
0364         r |= 1 << gpio2;
0365     else
0366         r &= ~(1 << gpio2);
0367     __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
0368     wmb();
0369 }
0370 
0371 /**
0372  * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
0373  * @gpio2:  The GPIO2 pin to activate (200...215).
0374  *
0375  * GPIO208-215 have one shared interrupt line to the INTC.  They are
0376  * and'ed with a per-pin enable bit and finally or'ed together to form
0377  * a single irq request (useful for active-high sources).
0378  * With this function, a pins' individual contribution to the int request
0379  * can be enabled.  As with all other GPIO-based interrupts, the INTC
0380  * must be programmed to accept the GPIO208_215 interrupt as well.
0381  *
0382  * NOTE: Calling this macro is only necessary for GPIO208-215; all other
0383  * GPIO2-based interrupts have their own request to the INTC.  Please
0384  * consult your Alchemy databook for more information!
0385  *
0386  * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
0387  * line to the INTC, GPIO201_205.  This function can be used for those
0388  * as well.
0389  *
0390  * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
0391  * (200-215 by default). No sanity checks are made,
0392  */
0393 static inline void alchemy_gpio2_enable_int(int gpio2)
0394 {
0395     unsigned long flags;
0396 
0397     gpio2 -= ALCHEMY_GPIO2_BASE;
0398 
0399     /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
0400     switch (alchemy_get_cputype()) {
0401     case ALCHEMY_CPU_AU1100:
0402     case ALCHEMY_CPU_AU1500:
0403         gpio2 -= 8;
0404     }
0405 
0406     local_irq_save(flags);
0407     __alchemy_gpio2_mod_int(gpio2, 1);
0408     local_irq_restore(flags);
0409 }
0410 
0411 /**
0412  * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
0413  * @gpio2:  The GPIO2 pin to activate (200...215).
0414  *
0415  * see function alchemy_gpio2_enable_int() for more information.
0416  */
0417 static inline void alchemy_gpio2_disable_int(int gpio2)
0418 {
0419     unsigned long flags;
0420 
0421     gpio2 -= ALCHEMY_GPIO2_BASE;
0422 
0423     /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
0424     switch (alchemy_get_cputype()) {
0425     case ALCHEMY_CPU_AU1100:
0426     case ALCHEMY_CPU_AU1500:
0427         gpio2 -= 8;
0428     }
0429 
0430     local_irq_save(flags);
0431     __alchemy_gpio2_mod_int(gpio2, 0);
0432     local_irq_restore(flags);
0433 }
0434 
0435 /**
0436  * alchemy_gpio2_enable -  Activate GPIO2 block.
0437  *
0438  * The GPIO2 block must be enabled excplicitly to work.  On systems
0439  * where this isn't done by the bootloader, this macro can be used.
0440  */
0441 static inline void alchemy_gpio2_enable(void)
0442 {
0443     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0444     __raw_writel(3, base + AU1000_GPIO2_ENABLE);    /* reset, clock enabled */
0445     wmb();
0446     __raw_writel(1, base + AU1000_GPIO2_ENABLE);    /* clock enabled */
0447     wmb();
0448 }
0449 
0450 /**
0451  * alchemy_gpio2_disable - disable GPIO2 block.
0452  *
0453  * Disable and put GPIO2 block in low-power mode.
0454  */
0455 static inline void alchemy_gpio2_disable(void)
0456 {
0457     void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
0458     __raw_writel(2, base + AU1000_GPIO2_ENABLE);    /* reset, clock disabled */
0459     wmb();
0460 }
0461 
0462 /**********************************************************************/
0463 
0464 /* wrappers for on-chip gpios; can be used before gpio chips have been
0465  * registered with gpiolib.
0466  */
0467 static inline int alchemy_gpio_direction_input(int gpio)
0468 {
0469     return (gpio >= ALCHEMY_GPIO2_BASE) ?
0470         alchemy_gpio2_direction_input(gpio) :
0471         alchemy_gpio1_direction_input(gpio);
0472 }
0473 
0474 static inline int alchemy_gpio_direction_output(int gpio, int v)
0475 {
0476     return (gpio >= ALCHEMY_GPIO2_BASE) ?
0477         alchemy_gpio2_direction_output(gpio, v) :
0478         alchemy_gpio1_direction_output(gpio, v);
0479 }
0480 
0481 static inline int alchemy_gpio_get_value(int gpio)
0482 {
0483     return (gpio >= ALCHEMY_GPIO2_BASE) ?
0484         alchemy_gpio2_get_value(gpio) :
0485         alchemy_gpio1_get_value(gpio);
0486 }
0487 
0488 static inline void alchemy_gpio_set_value(int gpio, int v)
0489 {
0490     if (gpio >= ALCHEMY_GPIO2_BASE)
0491         alchemy_gpio2_set_value(gpio, v);
0492     else
0493         alchemy_gpio1_set_value(gpio, v);
0494 }
0495 
0496 static inline int alchemy_gpio_is_valid(int gpio)
0497 {
0498     return (gpio >= ALCHEMY_GPIO2_BASE) ?
0499         alchemy_gpio2_is_valid(gpio) :
0500         alchemy_gpio1_is_valid(gpio);
0501 }
0502 
0503 static inline int alchemy_gpio_cansleep(int gpio)
0504 {
0505     return 0;   /* Alchemy never gets tired */
0506 }
0507 
0508 static inline int alchemy_gpio_to_irq(int gpio)
0509 {
0510     return (gpio >= ALCHEMY_GPIO2_BASE) ?
0511         alchemy_gpio2_to_irq(gpio) :
0512         alchemy_gpio1_to_irq(gpio);
0513 }
0514 
0515 static inline int alchemy_irq_to_gpio(int irq)
0516 {
0517     switch (alchemy_get_cputype()) {
0518     case ALCHEMY_CPU_AU1000:
0519         return au1000_irq_to_gpio(irq);
0520     case ALCHEMY_CPU_AU1100:
0521         return au1100_irq_to_gpio(irq);
0522     case ALCHEMY_CPU_AU1500:
0523         return au1500_irq_to_gpio(irq);
0524     case ALCHEMY_CPU_AU1550:
0525         return au1550_irq_to_gpio(irq);
0526     case ALCHEMY_CPU_AU1200:
0527         return au1200_irq_to_gpio(irq);
0528     }
0529     return -ENXIO;
0530 }
0531 
0532 #endif /* _ALCHEMY_GPIO_AU1000_H_ */
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