asm/mach-au1x00/au1xxx_dbdma.h

0001 /*
0002  *
0003  * BRIEF MODULE DESCRIPTION
0004  *  Include file for Alchemy Semiconductor's Au1550 Descriptor
0005  *  Based DMA Controller.
0006  *
0007  * Copyright 2004 Embedded Edge, LLC
0008  *  dan@embeddededge.com
0009  *
0010  *  This program is free software; you can redistribute  it and/or modify it
0011  *  under  the terms of  the GNU General  Public License as published by the
0012  *  Free Software Foundation;  either version 2 of the  License, or (at your
0013  *  option) any later version.
0014  *
0015  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0016  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0017  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0018  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0019  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0020  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0021  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0022  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0023  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0024  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0025  *
0026  *  You should have received a copy of the  GNU General Public License along
0027  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0028  *  675 Mass Ave, Cambridge, MA 02139, USA.
0029  */
0030
0031 /*
0032  * Specifics for the Au1xxx Descriptor-Based DMA Controller,
0033  * first seen in the AU1550 part.
0034  */
0035 #ifndef _AU1000_DBDMA_H_
0036 #define _AU1000_DBDMA_H_
0037
0038 #ifndef _LANGUAGE_ASSEMBLY
0039
0040 typedef volatile struct dbdma_global {
0041     u32 ddma_config;
0042     u32 ddma_intstat;
0043     u32 ddma_throttle;
0044     u32 ddma_inten;
0045 } dbdma_global_t;
0046
0047 /* General Configuration. */
0048 #define DDMA_CONFIG_AF      (1 << 2)
0049 #define DDMA_CONFIG_AH      (1 << 1)
0050 #define DDMA_CONFIG_AL      (1 << 0)
0051
0052 #define DDMA_THROTTLE_EN    (1 << 31)
0053
0054 /* The structure of a DMA Channel. */
0055 typedef volatile struct au1xxx_dma_channel {
0056     u32 ddma_cfg;   /* See below */
0057     u32 ddma_desptr;    /* 32-byte aligned pointer to descriptor */
0058     u32 ddma_statptr;   /* word aligned pointer to status word */
0059     u32 ddma_dbell; /* A write activates channel operation */
0060     u32 ddma_irq;   /* If bit 0 set, interrupt pending */
0061     u32 ddma_stat;  /* See below */
0062     u32 ddma_bytecnt;   /* Byte count, valid only when chan idle */
0063     /* Remainder, up to the 256 byte boundary, is reserved. */
0064 } au1x_dma_chan_t;
0065
0066 #define DDMA_CFG_SED    (1 << 9)    /* source DMA level/edge detect */
0067 #define DDMA_CFG_SP (1 << 8)    /* source DMA polarity */
0068 #define DDMA_CFG_DED    (1 << 7)    /* destination DMA level/edge detect */
0069 #define DDMA_CFG_DP (1 << 6)    /* destination DMA polarity */
0070 #define DDMA_CFG_SYNC   (1 << 5)    /* Sync static bus controller */
0071 #define DDMA_CFG_PPR    (1 << 4)    /* PCI posted read/write control */
0072 #define DDMA_CFG_DFN    (1 << 3)    /* Descriptor fetch non-coherent */
0073 #define DDMA_CFG_SBE    (1 << 2)    /* Source big endian */
0074 #define DDMA_CFG_DBE    (1 << 1)    /* Destination big endian */
0075 #define DDMA_CFG_EN (1 << 0)    /* Channel enable */
0076
0077 /*
0078  * Always set when descriptor processing done, regardless of
0079  * interrupt enable state.  Reflected in global intstat, don't
0080  * clear this until global intstat is read/used.
0081  */
0082 #define DDMA_IRQ_IN (1 << 0)
0083
0084 #define DDMA_STAT_DB    (1 << 2)    /* Doorbell pushed */
0085 #define DDMA_STAT_V (1 << 1)    /* Descriptor valid */
0086 #define DDMA_STAT_H (1 << 0)    /* Channel Halted */
0087
0088 /*
0089  * "Standard" DDMA Descriptor.
0090  * Must be 32-byte aligned.
0091  */
0092 typedef volatile struct au1xxx_ddma_desc {
0093     u32 dscr_cmd0;      /* See below */
0094     u32 dscr_cmd1;      /* See below */
0095     u32 dscr_source0;       /* source phys address */
0096     u32 dscr_source1;       /* See below */
0097     u32 dscr_dest0;     /* Destination address */
0098     u32 dscr_dest1;     /* See below */
0099     u32 dscr_stat;      /* completion status */
0100     u32 dscr_nxtptr;        /* Next descriptor pointer (mostly) */
0101     /*
0102      * First 32 bytes are HW specific!!!
0103      * Let's have some SW data following -- make sure it's 32 bytes.
0104      */
0105     u32 sw_status;
0106     u32 sw_context;
0107     u32 sw_reserved[6];
0108 } au1x_ddma_desc_t;
0109
0110 #define DSCR_CMD0_V     (1 << 31)   /* Descriptor valid */
0111 #define DSCR_CMD0_MEM       (1 << 30)   /* mem-mem transfer */
0112 #define DSCR_CMD0_SID_MASK  (0x1f << 25)    /* Source ID */
0113 #define DSCR_CMD0_DID_MASK  (0x1f << 20)    /* Destination ID */
0114 #define DSCR_CMD0_SW_MASK   (0x3 << 18) /* Source Width */
0115 #define DSCR_CMD0_DW_MASK   (0x3 << 16) /* Destination Width */
0116 #define DSCR_CMD0_ARB       (0x1 << 15) /* Set for Hi Pri */
0117 #define DSCR_CMD0_DT_MASK   (0x3 << 13) /* Descriptor Type */
0118 #define DSCR_CMD0_SN        (0x1 << 12) /* Source non-coherent */
0119 #define DSCR_CMD0_DN        (0x1 << 11) /* Destination non-coherent */
0120 #define DSCR_CMD0_SM        (0x1 << 10) /* Stride mode */
0121 #define DSCR_CMD0_IE        (0x1 << 8)  /* Interrupt Enable */
0122 #define DSCR_CMD0_SP        (0x1 << 4)  /* Status pointer select */
0123 #define DSCR_CMD0_CV        (0x1 << 2)  /* Clear Valid when done */
0124 #define DSCR_CMD0_ST_MASK   (0x3 << 0)  /* Status instruction */
0125
0126 #define SW_STATUS_INUSE     (1 << 0)
0127
0128 /* Command 0 device IDs. */
0129 #define AU1550_DSCR_CMD0_UART0_TX   0
0130 #define AU1550_DSCR_CMD0_UART0_RX   1
0131 #define AU1550_DSCR_CMD0_UART3_TX   2
0132 #define AU1550_DSCR_CMD0_UART3_RX   3
0133 #define AU1550_DSCR_CMD0_DMA_REQ0   4
0134 #define AU1550_DSCR_CMD0_DMA_REQ1   5
0135 #define AU1550_DSCR_CMD0_DMA_REQ2   6
0136 #define AU1550_DSCR_CMD0_DMA_REQ3   7
0137 #define AU1550_DSCR_CMD0_USBDEV_RX0 8
0138 #define AU1550_DSCR_CMD0_USBDEV_TX0 9
0139 #define AU1550_DSCR_CMD0_USBDEV_TX1 10
0140 #define AU1550_DSCR_CMD0_USBDEV_TX2 11
0141 #define AU1550_DSCR_CMD0_USBDEV_RX3 12
0142 #define AU1550_DSCR_CMD0_USBDEV_RX4 13
0143 #define AU1550_DSCR_CMD0_PSC0_TX    14
0144 #define AU1550_DSCR_CMD0_PSC0_RX    15
0145 #define AU1550_DSCR_CMD0_PSC1_TX    16
0146 #define AU1550_DSCR_CMD0_PSC1_RX    17
0147 #define AU1550_DSCR_CMD0_PSC2_TX    18
0148 #define AU1550_DSCR_CMD0_PSC2_RX    19
0149 #define AU1550_DSCR_CMD0_PSC3_TX    20
0150 #define AU1550_DSCR_CMD0_PSC3_RX    21
0151 #define AU1550_DSCR_CMD0_PCI_WRITE  22
0152 #define AU1550_DSCR_CMD0_NAND_FLASH 23
0153 #define AU1550_DSCR_CMD0_MAC0_RX    24
0154 #define AU1550_DSCR_CMD0_MAC0_TX    25
0155 #define AU1550_DSCR_CMD0_MAC1_RX    26
0156 #define AU1550_DSCR_CMD0_MAC1_TX    27
0157
0158 #define AU1200_DSCR_CMD0_UART0_TX   0
0159 #define AU1200_DSCR_CMD0_UART0_RX   1
0160 #define AU1200_DSCR_CMD0_UART1_TX   2
0161 #define AU1200_DSCR_CMD0_UART1_RX   3
0162 #define AU1200_DSCR_CMD0_DMA_REQ0   4
0163 #define AU1200_DSCR_CMD0_DMA_REQ1   5
0164 #define AU1200_DSCR_CMD0_MAE_BE     6
0165 #define AU1200_DSCR_CMD0_MAE_FE     7
0166 #define AU1200_DSCR_CMD0_SDMS_TX0   8
0167 #define AU1200_DSCR_CMD0_SDMS_RX0   9
0168 #define AU1200_DSCR_CMD0_SDMS_TX1   10
0169 #define AU1200_DSCR_CMD0_SDMS_RX1   11
0170 #define AU1200_DSCR_CMD0_AES_TX     13
0171 #define AU1200_DSCR_CMD0_AES_RX     12
0172 #define AU1200_DSCR_CMD0_PSC0_TX    14
0173 #define AU1200_DSCR_CMD0_PSC0_RX    15
0174 #define AU1200_DSCR_CMD0_PSC1_TX    16
0175 #define AU1200_DSCR_CMD0_PSC1_RX    17
0176 #define AU1200_DSCR_CMD0_CIM_RXA    18
0177 #define AU1200_DSCR_CMD0_CIM_RXB    19
0178 #define AU1200_DSCR_CMD0_CIM_RXC    20
0179 #define AU1200_DSCR_CMD0_MAE_BOTH   21
0180 #define AU1200_DSCR_CMD0_LCD        22
0181 #define AU1200_DSCR_CMD0_NAND_FLASH 23
0182 #define AU1200_DSCR_CMD0_PSC0_SYNC  24
0183 #define AU1200_DSCR_CMD0_PSC1_SYNC  25
0184 #define AU1200_DSCR_CMD0_CIM_SYNC   26
0185
0186 #define AU1300_DSCR_CMD0_UART0_TX      0
0187 #define AU1300_DSCR_CMD0_UART0_RX      1
0188 #define AU1300_DSCR_CMD0_UART1_TX      2
0189 #define AU1300_DSCR_CMD0_UART1_RX      3
0190 #define AU1300_DSCR_CMD0_UART2_TX      4
0191 #define AU1300_DSCR_CMD0_UART2_RX      5
0192 #define AU1300_DSCR_CMD0_UART3_TX      6
0193 #define AU1300_DSCR_CMD0_UART3_RX      7
0194 #define AU1300_DSCR_CMD0_SDMS_TX0      8
0195 #define AU1300_DSCR_CMD0_SDMS_RX0      9
0196 #define AU1300_DSCR_CMD0_SDMS_TX1      10
0197 #define AU1300_DSCR_CMD0_SDMS_RX1      11
0198 #define AU1300_DSCR_CMD0_AES_TX        12
0199 #define AU1300_DSCR_CMD0_AES_RX        13
0200 #define AU1300_DSCR_CMD0_PSC0_TX       14
0201 #define AU1300_DSCR_CMD0_PSC0_RX       15
0202 #define AU1300_DSCR_CMD0_PSC1_TX       16
0203 #define AU1300_DSCR_CMD0_PSC1_RX       17
0204 #define AU1300_DSCR_CMD0_PSC2_TX       18
0205 #define AU1300_DSCR_CMD0_PSC2_RX       19
0206 #define AU1300_DSCR_CMD0_PSC3_TX       20
0207 #define AU1300_DSCR_CMD0_PSC3_RX       21
0208 #define AU1300_DSCR_CMD0_LCD           22
0209 #define AU1300_DSCR_CMD0_NAND_FLASH    23
0210 #define AU1300_DSCR_CMD0_SDMS_TX2      24
0211 #define AU1300_DSCR_CMD0_SDMS_RX2      25
0212 #define AU1300_DSCR_CMD0_CIM_SYNC      26
0213 #define AU1300_DSCR_CMD0_UDMA          27
0214 #define AU1300_DSCR_CMD0_DMA_REQ0      28
0215 #define AU1300_DSCR_CMD0_DMA_REQ1      29
0216
0217 #define DSCR_CMD0_THROTTLE  30
0218 #define DSCR_CMD0_ALWAYS    31
0219 #define DSCR_NDEV_IDS       32
0220 /* This macro is used to find/create custom device types */
0221 #define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
0222                   ((d) & 0xFF))
0223 #define DSCR_CUSTOM2DEV_ID(x)   ((x) & 0xFF)
0224
0225 #define DSCR_CMD0_SID(x)    (((x) & 0x1f) << 25)
0226 #define DSCR_CMD0_DID(x)    (((x) & 0x1f) << 20)
0227
0228 /* Source/Destination transfer width. */
0229 #define DSCR_CMD0_BYTE      0
0230 #define DSCR_CMD0_HALFWORD  1
0231 #define DSCR_CMD0_WORD      2
0232
0233 #define DSCR_CMD0_SW(x)     (((x) & 0x3) << 18)
0234 #define DSCR_CMD0_DW(x)     (((x) & 0x3) << 16)
0235
0236 /* DDMA Descriptor Type. */
0237 #define DSCR_CMD0_STANDARD  0
0238 #define DSCR_CMD0_LITERAL   1
0239 #define DSCR_CMD0_CMP_BRANCH    2
0240
0241 #define DSCR_CMD0_DT(x)     (((x) & 0x3) << 13)
0242
0243 /* Status Instruction. */
0244 #define DSCR_CMD0_ST_NOCHANGE   0   /* Don't change */
0245 #define DSCR_CMD0_ST_CURRENT    1   /* Write current status */
0246 #define DSCR_CMD0_ST_CMD0   2   /* Write cmd0 with V cleared */
0247 #define DSCR_CMD0_ST_BYTECNT    3   /* Write remaining byte count */
0248
0249 #define DSCR_CMD0_ST(x)     (((x) & 0x3) << 0)
0250
0251 /* Descriptor Command 1. */
0252 #define DSCR_CMD1_SUPTR_MASK    (0xf << 28) /* upper 4 bits of src addr */
0253 #define DSCR_CMD1_DUPTR_MASK    (0xf << 24) /* upper 4 bits of dest addr */
0254 #define DSCR_CMD1_FL_MASK   (0x3 << 22) /* Flag bits */
0255 #define DSCR_CMD1_BC_MASK   (0x3fffff)  /* Byte count */
0256
0257 /* Flag description. */
0258 #define DSCR_CMD1_FL_MEM_STRIDE0    0
0259 #define DSCR_CMD1_FL_MEM_STRIDE1    1
0260 #define DSCR_CMD1_FL_MEM_STRIDE2    2
0261
0262 #define DSCR_CMD1_FL(x)     (((x) & 0x3) << 22)
0263
0264 /* Source1, 1-dimensional stride. */
0265 #define DSCR_SRC1_STS_MASK  (3 << 30)   /* Src xfer size */
0266 #define DSCR_SRC1_SAM_MASK  (3 << 28)   /* Src xfer movement */
0267 #define DSCR_SRC1_SB_MASK   (0x3fff << 14)  /* Block size */
0268 #define DSCR_SRC1_SB(x)     (((x) & 0x3fff) << 14)
0269 #define DSCR_SRC1_SS_MASK   (0x3fff << 0)   /* Stride */
0270 #define DSCR_SRC1_SS(x)     (((x) & 0x3fff) << 0)
0271
0272 /* Dest1, 1-dimensional stride. */
0273 #define DSCR_DEST1_DTS_MASK (3 << 30)   /* Dest xfer size */
0274 #define DSCR_DEST1_DAM_MASK (3 << 28)   /* Dest xfer movement */
0275 #define DSCR_DEST1_DB_MASK  (0x3fff << 14)  /* Block size */
0276 #define DSCR_DEST1_DB(x)    (((x) & 0x3fff) << 14)
0277 #define DSCR_DEST1_DS_MASK  (0x3fff << 0)   /* Stride */
0278 #define DSCR_DEST1_DS(x)    (((x) & 0x3fff) << 0)
0279
0280 #define DSCR_xTS_SIZE1      0
0281 #define DSCR_xTS_SIZE2      1
0282 #define DSCR_xTS_SIZE4      2
0283 #define DSCR_xTS_SIZE8      3
0284 #define DSCR_SRC1_STS(x)    (((x) & 3) << 30)
0285 #define DSCR_DEST1_DTS(x)   (((x) & 3) << 30)
0286
0287 #define DSCR_xAM_INCREMENT  0
0288 #define DSCR_xAM_DECREMENT  1
0289 #define DSCR_xAM_STATIC     2
0290 #define DSCR_xAM_BURST      3
0291 #define DSCR_SRC1_SAM(x)    (((x) & 3) << 28)
0292 #define DSCR_DEST1_DAM(x)   (((x) & 3) << 28)
0293
0294 /* The next descriptor pointer. */
0295 #define DSCR_NXTPTR_MASK    (0x07ffffff)
0296 #define DSCR_NXTPTR(x)      ((x) >> 5)
0297 #define DSCR_GET_NXTPTR(x)  ((x) << 5)
0298 #define DSCR_NXTPTR_MS      (1 << 27)
0299
0300 /* The number of DBDMA channels. */
0301 #define NUM_DBDMA_CHANS 16
0302
0303 /*
0304  * DDMA API definitions
0305  * FIXME: may not fit to this header file
0306  */
0307 typedef struct dbdma_device_table {
0308     u32 dev_id;
0309     u32 dev_flags;
0310     u32 dev_tsize;
0311     u32 dev_devwidth;
0312     u32 dev_physaddr;       /* If FIFO */
0313     u32 dev_intlevel;
0314     u32 dev_intpolarity;
0315 } dbdev_tab_t;
0316
0317
0318 typedef struct dbdma_chan_config {
0319     spinlock_t  lock;
0320
0321     u32         chan_flags;
0322     u32         chan_index;
0323     dbdev_tab_t     *chan_src;
0324     dbdev_tab_t     *chan_dest;
0325     au1x_dma_chan_t     *chan_ptr;
0326     au1x_ddma_desc_t    *chan_desc_base;
0327     u32         cdb_membase; /* kmalloc base of above */
0328     au1x_ddma_desc_t    *get_ptr, *put_ptr, *cur_ptr;
0329     void            *chan_callparam;
0330     void            (*chan_callback)(int, void *);
0331 } chan_tab_t;
0332
0333 #define DEV_FLAGS_INUSE     (1 << 0)
0334 #define DEV_FLAGS_ANYUSE    (1 << 1)
0335 #define DEV_FLAGS_OUT       (1 << 2)
0336 #define DEV_FLAGS_IN        (1 << 3)
0337 #define DEV_FLAGS_BURSTABLE (1 << 4)
0338 #define DEV_FLAGS_SYNC      (1 << 5)
0339 /* end DDMA API definitions */
0340
0341 /*
0342  * External functions for drivers to use.
0343  * Use this to allocate a DBDMA channel.  The device IDs are one of
0344  * the DSCR_CMD0 devices IDs, which is usually redefined to a more
0345  * meaningful name.  The 'callback' is called during DMA completion
0346  * interrupt.
0347  */
0348 extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
0349                    void (*callback)(int, void *),
0350                    void *callparam);
0351
0352 #define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
0353
0354 /* Set the device width of an in/out FIFO. */
0355 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
0356
0357 /* Allocate a ring of descriptors for DBDMA. */
0358 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
0359
0360 /* Put buffers on source/destination descriptors. */
0361 u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
0362 u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
0363
0364 /* Get a buffer from the destination descriptor. */
0365 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
0366
0367 void au1xxx_dbdma_stop(u32 chanid);
0368 void au1xxx_dbdma_start(u32 chanid);
0369 void au1xxx_dbdma_reset(u32 chanid);
0370 u32 au1xxx_get_dma_residue(u32 chanid);
0371
0372 void au1xxx_dbdma_chan_free(u32 chanid);
0373 void au1xxx_dbdma_dump(u32 chanid);
0374
0375 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
0376
0377 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
0378 extern void au1xxx_ddma_del_device(u32 devid);
0379 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
0380
0381 /*
0382  *  Flags for the put_source/put_dest functions.
0383  */
0384 #define DDMA_FLAGS_IE   (1 << 0)
0385 #define DDMA_FLAGS_NOIE (1 << 1)
0386
0387 #endif /* _LANGUAGE_ASSEMBLY */
0388 #endif /* _AU1000_DBDMA_H_ */