asm/mach-au1x00/au1100_mmc.h

0001 /*
0002  * BRIEF MODULE DESCRIPTION
0003  *  Defines for using the MMC/SD controllers on the
0004  *      Alchemy Au1100 mips processor.
0005  *
0006  * Copyright (c) 2003 Embedded Edge, LLC.
0007  * Author: Embedded Edge, LLC.
0008  *          dan@embeddededge.com or tim@embeddededge.com
0009  *
0010  *  This program is free software; you can redistribute  it and/or modify it
0011  *  under  the terms of  the GNU General  Public License as published by the
0012  *  Free Software Foundation;  either version 2 of the  License, or (at your
0013  *  option) any later version.
0014  *
0015  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0016  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0017  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0018  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0019  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0020  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0021  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0022  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0023  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0024  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0025  *
0026  *  You should have received a copy of the  GNU General Public License along
0027  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0028  *  675 Mass Ave, Cambridge, MA 02139, USA.
0029  *
0030  */
0031 /*
0032  * AU1100 MMC/SD definitions.
0033  *
0034  * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
0035  *    June, 2003
0036  */
0037
0038 #ifndef __ASM_AU1100_MMC_H
0039 #define __ASM_AU1100_MMC_H
0040
0041 #include <linux/leds.h>
0042
0043 struct au1xmmc_platform_data {
0044     int(*cd_setup)(void *mmc_host, int on);
0045     int(*card_inserted)(void *mmc_host);
0046     int(*card_readonly)(void *mmc_host);
0047     void(*set_power)(void *mmc_host, int state);
0048     struct led_classdev *led;
0049     unsigned long mask_host_caps;
0050 };
0051
0052 #define SD0_BASE    0xB0600000
0053 #define SD1_BASE    0xB0680000
0054
0055
0056 /*
0057  *  Register offsets.
0058  */
0059 #define SD_TXPORT   (0x0000)
0060 #define SD_RXPORT   (0x0004)
0061 #define SD_CONFIG   (0x0008)
0062 #define SD_ENABLE   (0x000C)
0063 #define SD_CONFIG2  (0x0010)
0064 #define SD_BLKSIZE  (0x0014)
0065 #define SD_STATUS   (0x0018)
0066 #define SD_DEBUG    (0x001C)
0067 #define SD_CMD      (0x0020)
0068 #define SD_CMDARG   (0x0024)
0069 #define SD_RESP3    (0x0028)
0070 #define SD_RESP2    (0x002C)
0071 #define SD_RESP1    (0x0030)
0072 #define SD_RESP0    (0x0034)
0073 #define SD_TIMEOUT  (0x0038)
0074
0075
0076 /*
0077  *  SD_TXPORT bit definitions.
0078  */
0079 #define SD_TXPORT_TXD   (0x000000ff)
0080
0081
0082 /*
0083  *  SD_RXPORT bit definitions.
0084  */
0085 #define SD_RXPORT_RXD   (0x000000ff)
0086
0087
0088 /*
0089  *  SD_CONFIG bit definitions.
0090  */
0091 #define SD_CONFIG_DIV   (0x000001ff)
0092 #define SD_CONFIG_DE    (0x00000200)
0093 #define SD_CONFIG_NE    (0x00000400)
0094 #define SD_CONFIG_TU    (0x00000800)
0095 #define SD_CONFIG_TO    (0x00001000)
0096 #define SD_CONFIG_RU    (0x00002000)
0097 #define SD_CONFIG_RO    (0x00004000)
0098 #define SD_CONFIG_I (0x00008000)
0099 #define SD_CONFIG_CR    (0x00010000)
0100 #define SD_CONFIG_RAT   (0x00020000)
0101 #define SD_CONFIG_DD    (0x00040000)
0102 #define SD_CONFIG_DT    (0x00080000)
0103 #define SD_CONFIG_SC    (0x00100000)
0104 #define SD_CONFIG_RC    (0x00200000)
0105 #define SD_CONFIG_WC    (0x00400000)
0106 #define SD_CONFIG_xxx   (0x00800000)
0107 #define SD_CONFIG_TH    (0x01000000)
0108 #define SD_CONFIG_TE    (0x02000000)
0109 #define SD_CONFIG_TA    (0x04000000)
0110 #define SD_CONFIG_RH    (0x08000000)
0111 #define SD_CONFIG_RA    (0x10000000)
0112 #define SD_CONFIG_RF    (0x20000000)
0113 #define SD_CONFIG_CD    (0x40000000)
0114 #define SD_CONFIG_SI    (0x80000000)
0115
0116
0117 /*
0118  *  SD_ENABLE bit definitions.
0119  */
0120 #define SD_ENABLE_CE    (0x00000001)
0121 #define SD_ENABLE_R (0x00000002)
0122
0123
0124 /*
0125  *  SD_CONFIG2 bit definitions.
0126  */
0127 #define SD_CONFIG2_EN   (0x00000001)
0128 #define SD_CONFIG2_FF   (0x00000002)
0129 #define SD_CONFIG2_xx1  (0x00000004)
0130 #define SD_CONFIG2_DF   (0x00000008)
0131 #define SD_CONFIG2_DC   (0x00000010)
0132 #define SD_CONFIG2_xx2  (0x000000e0)
0133 #define SD_CONFIG2_BB   (0x00000080)
0134 #define SD_CONFIG2_WB   (0x00000100)
0135 #define SD_CONFIG2_RW   (0x00000200)
0136 #define SD_CONFIG2_DP   (0x00000400)
0137
0138
0139 /*
0140  *  SD_BLKSIZE bit definitions.
0141  */
0142 #define SD_BLKSIZE_BS   (0x000007ff)
0143 #define SD_BLKSIZE_BS_SHIFT  (0)
0144 #define SD_BLKSIZE_BC   (0x01ff0000)
0145 #define SD_BLKSIZE_BC_SHIFT (16)
0146
0147
0148 /*
0149  *  SD_STATUS bit definitions.
0150  */
0151 #define SD_STATUS_DCRCW (0x00000007)
0152 #define SD_STATUS_xx1   (0x00000008)
0153 #define SD_STATUS_CB    (0x00000010)
0154 #define SD_STATUS_DB    (0x00000020)
0155 #define SD_STATUS_CF    (0x00000040)
0156 #define SD_STATUS_D3    (0x00000080)
0157 #define SD_STATUS_xx2   (0x00000300)
0158 #define SD_STATUS_NE    (0x00000400)
0159 #define SD_STATUS_TU    (0x00000800)
0160 #define SD_STATUS_TO    (0x00001000)
0161 #define SD_STATUS_RU    (0x00002000)
0162 #define SD_STATUS_RO    (0x00004000)
0163 #define SD_STATUS_I (0x00008000)
0164 #define SD_STATUS_CR    (0x00010000)
0165 #define SD_STATUS_RAT   (0x00020000)
0166 #define SD_STATUS_DD    (0x00040000)
0167 #define SD_STATUS_DT    (0x00080000)
0168 #define SD_STATUS_SC    (0x00100000)
0169 #define SD_STATUS_RC    (0x00200000)
0170 #define SD_STATUS_WC    (0x00400000)
0171 #define SD_STATUS_xx3   (0x00800000)
0172 #define SD_STATUS_TH    (0x01000000)
0173 #define SD_STATUS_TE    (0x02000000)
0174 #define SD_STATUS_TA    (0x04000000)
0175 #define SD_STATUS_RH    (0x08000000)
0176 #define SD_STATUS_RA    (0x10000000)
0177 #define SD_STATUS_RF    (0x20000000)
0178 #define SD_STATUS_CD    (0x40000000)
0179 #define SD_STATUS_SI    (0x80000000)
0180
0181
0182 /*
0183  *  SD_CMD bit definitions.
0184  */
0185 #define SD_CMD_GO   (0x00000001)
0186 #define SD_CMD_RY   (0x00000002)
0187 #define SD_CMD_xx1  (0x0000000c)
0188 #define SD_CMD_CT_MASK  (0x000000f0)
0189 #define SD_CMD_CT_0 (0x00000000)
0190 #define SD_CMD_CT_1 (0x00000010)
0191 #define SD_CMD_CT_2 (0x00000020)
0192 #define SD_CMD_CT_3 (0x00000030)
0193 #define SD_CMD_CT_4 (0x00000040)
0194 #define SD_CMD_CT_5 (0x00000050)
0195 #define SD_CMD_CT_6 (0x00000060)
0196 #define SD_CMD_CT_7 (0x00000070)
0197 #define SD_CMD_CI   (0x0000ff00)
0198 #define SD_CMD_CI_SHIFT     (8)
0199 #define SD_CMD_RT_MASK  (0x00ff0000)
0200 #define SD_CMD_RT_0 (0x00000000)
0201 #define SD_CMD_RT_1 (0x00010000)
0202 #define SD_CMD_RT_2 (0x00020000)
0203 #define SD_CMD_RT_3 (0x00030000)
0204 #define SD_CMD_RT_4 (0x00040000)
0205 #define SD_CMD_RT_5 (0x00050000)
0206 #define SD_CMD_RT_6 (0x00060000)
0207 #define SD_CMD_RT_1B    (0x00810000)
0208
0209
0210 #endif /* __ASM_AU1100_MMC_H */