asm/mach-ath79/ath79.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Atheros AR71XX/AR724X/AR913X common definitions
0004  *
0005  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0006  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0007  *
0008  *  Parts of this file are based on Atheros' 2.6.15 BSP
0009  */
0010
0011 #ifndef __ASM_MACH_ATH79_H
0012 #define __ASM_MACH_ATH79_H
0013
0014 #include <linux/types.h>
0015 #include <linux/io.h>
0016
0017 enum ath79_soc_type {
0018     ATH79_SOC_UNKNOWN,
0019     ATH79_SOC_AR7130,
0020     ATH79_SOC_AR7141,
0021     ATH79_SOC_AR7161,
0022     ATH79_SOC_AR7240,
0023     ATH79_SOC_AR7241,
0024     ATH79_SOC_AR7242,
0025     ATH79_SOC_AR9130,
0026     ATH79_SOC_AR9132,
0027     ATH79_SOC_AR9330,
0028     ATH79_SOC_AR9331,
0029     ATH79_SOC_AR9341,
0030     ATH79_SOC_AR9342,
0031     ATH79_SOC_AR9344,
0032     ATH79_SOC_QCA9533,
0033     ATH79_SOC_QCA9556,
0034     ATH79_SOC_QCA9558,
0035     ATH79_SOC_TP9343,
0036     ATH79_SOC_QCA956X,
0037 };
0038
0039 extern enum ath79_soc_type ath79_soc;
0040 extern unsigned int ath79_soc_rev;
0041
0042 static inline int soc_is_ar71xx(void)
0043 {
0044     return (ath79_soc == ATH79_SOC_AR7130 ||
0045         ath79_soc == ATH79_SOC_AR7141 ||
0046         ath79_soc == ATH79_SOC_AR7161);
0047 }
0048
0049 static inline int soc_is_ar724x(void)
0050 {
0051     return (ath79_soc == ATH79_SOC_AR7240 ||
0052         ath79_soc == ATH79_SOC_AR7241 ||
0053         ath79_soc == ATH79_SOC_AR7242);
0054 }
0055
0056 static inline int soc_is_ar7240(void)
0057 {
0058     return (ath79_soc == ATH79_SOC_AR7240);
0059 }
0060
0061 static inline int soc_is_ar7241(void)
0062 {
0063     return (ath79_soc == ATH79_SOC_AR7241);
0064 }
0065
0066 static inline int soc_is_ar7242(void)
0067 {
0068     return (ath79_soc == ATH79_SOC_AR7242);
0069 }
0070
0071 static inline int soc_is_ar913x(void)
0072 {
0073     return (ath79_soc == ATH79_SOC_AR9130 ||
0074         ath79_soc == ATH79_SOC_AR9132);
0075 }
0076
0077 static inline int soc_is_ar933x(void)
0078 {
0079     return (ath79_soc == ATH79_SOC_AR9330 ||
0080         ath79_soc == ATH79_SOC_AR9331);
0081 }
0082
0083 static inline int soc_is_ar9341(void)
0084 {
0085     return (ath79_soc == ATH79_SOC_AR9341);
0086 }
0087
0088 static inline int soc_is_ar9342(void)
0089 {
0090     return (ath79_soc == ATH79_SOC_AR9342);
0091 }
0092
0093 static inline int soc_is_ar9344(void)
0094 {
0095     return (ath79_soc == ATH79_SOC_AR9344);
0096 }
0097
0098 static inline int soc_is_ar934x(void)
0099 {
0100     return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
0101 }
0102
0103 static inline int soc_is_qca9533(void)
0104 {
0105     return ath79_soc == ATH79_SOC_QCA9533;
0106 }
0107
0108 static inline int soc_is_qca953x(void)
0109 {
0110     return soc_is_qca9533();
0111 }
0112
0113 static inline int soc_is_qca9556(void)
0114 {
0115     return ath79_soc == ATH79_SOC_QCA9556;
0116 }
0117
0118 static inline int soc_is_qca9558(void)
0119 {
0120     return ath79_soc == ATH79_SOC_QCA9558;
0121 }
0122
0123 static inline int soc_is_qca955x(void)
0124 {
0125     return soc_is_qca9556() || soc_is_qca9558();
0126 }
0127
0128 static inline int soc_is_tp9343(void)
0129 {
0130     return ath79_soc == ATH79_SOC_TP9343;
0131 }
0132
0133 static inline int soc_is_qca9561(void)
0134 {
0135     return ath79_soc == ATH79_SOC_QCA956X;
0136 }
0137
0138 static inline int soc_is_qca9563(void)
0139 {
0140     return ath79_soc == ATH79_SOC_QCA956X;
0141 }
0142
0143 static inline int soc_is_qca956x(void)
0144 {
0145     return soc_is_qca9561() || soc_is_qca9563();
0146 }
0147
0148 void ath79_ddr_wb_flush(unsigned int reg);
0149 void ath79_ddr_set_pci_windows(void);
0150
0151 extern void __iomem *ath79_pll_base;
0152 extern void __iomem *ath79_reset_base;
0153
0154 static inline void ath79_pll_wr(unsigned reg, u32 val)
0155 {
0156     __raw_writel(val, ath79_pll_base + reg);
0157 }
0158
0159 static inline u32 ath79_pll_rr(unsigned reg)
0160 {
0161     return __raw_readl(ath79_pll_base + reg);
0162 }
0163
0164 static inline void ath79_reset_wr(unsigned reg, u32 val)
0165 {
0166     __raw_writel(val, ath79_reset_base + reg);
0167     (void) __raw_readl(ath79_reset_base + reg); /* flush */
0168 }
0169
0170 static inline u32 ath79_reset_rr(unsigned reg)
0171 {
0172     return __raw_readl(ath79_reset_base + reg);
0173 }
0174
0175 void ath79_device_reset_set(u32 mask);
0176 void ath79_device_reset_clear(u32 mask);
0177
0178 #endif /* __ASM_MACH_ATH79_H */