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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Atheros AR231x/AR531x SoC specific CPU feature overrides
0004  *
0005  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
0006  *
0007  *  This file was derived from: include/asm-mips/cpu-features.h
0008  *  Copyright (C) 2003, 2004 Ralf Baechle
0009  *  Copyright (C) 2004 Maciej W. Rozycki
0010  */
0011 #ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
0012 #define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
0013 
0014 /*
0015  * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
0016  */
0017 #define cpu_has_tlb         1
0018 #define cpu_has_4kex            1
0019 #define cpu_has_3k_cache        0
0020 #define cpu_has_4k_cache        1
0021 #define cpu_has_sb1_cache       0
0022 #define cpu_has_fpu         0
0023 #define cpu_has_32fpr           0
0024 #define cpu_has_counter         1
0025 #define cpu_has_ejtag           1
0026 
0027 #if !defined(CONFIG_SOC_AR5312)
0028 #  define cpu_has_llsc          1
0029 #else
0030 /*
0031  * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
0032  * ll/sc instructions.
0033  */
0034 #  define cpu_has_llsc          0
0035 #endif
0036 
0037 #define cpu_has_mips16          0
0038 #define cpu_has_mips16e2        0
0039 #define cpu_has_mdmx            0
0040 #define cpu_has_mips3d          0
0041 #define cpu_has_smartmips       0
0042 
0043 #define cpu_has_mips32r1        1
0044 
0045 #if !defined(CONFIG_SOC_AR5312)
0046 #  define cpu_has_mips32r2      1
0047 #endif
0048 
0049 #define cpu_has_mips64r1        0
0050 #define cpu_has_mips64r2        0
0051 
0052 #define cpu_has_dsp         0
0053 #define cpu_has_mipsmt          0
0054 
0055 #define cpu_has_64bits          0
0056 #define cpu_has_64bit_zero_reg      0
0057 #define cpu_has_64bit_gp_regs       0
0058 
0059 #endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */