asm/mach-ar7/ar7.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
0005  */
0006
0007 #ifndef __AR7_H__
0008 #define __AR7_H__
0009
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/errno.h>
0013
0014 #include <asm/addrspace.h>
0015
0016 #define AR7_SDRAM_BASE  0x14000000
0017
0018 #define AR7_REGS_BASE   0x08610000
0019
0020 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
0021 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
0022 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
0023 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
0024 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
0025 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
0026 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
0027 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
0028 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
0029 #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
0030 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
0031 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
0032 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
0033 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
0034 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
0035 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
0036
0037 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
0038 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
0039 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
0040
0041 /* Titan registers */
0042 #define TITAN_REGS_ESWITCH_BASE (0x08640000)
0043 #define TITAN_REGS_MAC0     (TITAN_REGS_ESWITCH_BASE)
0044 #define TITAN_REGS_MAC1     (TITAN_REGS_ESWITCH_BASE + 0x0800)
0045 #define TITAN_REGS_MDIO     (TITAN_REGS_ESWITCH_BASE + 0x02000)
0046 #define TITAN_REGS_VLYNQ0   (AR7_REGS_BASE + 0x1c00)
0047 #define TITAN_REGS_VLYNQ1   (AR7_REGS_BASE + 0x1300)
0048
0049 #define AR7_RESET_PERIPHERAL    0x0
0050 #define AR7_RESET_SOFTWARE  0x4
0051 #define AR7_RESET_STATUS    0x8
0052
0053 #define AR7_RESET_BIT_CPMAC_LO  17
0054 #define AR7_RESET_BIT_CPMAC_HI  21
0055 #define AR7_RESET_BIT_MDIO  22
0056 #define AR7_RESET_BIT_EPHY  26
0057
0058 #define TITAN_RESET_BIT_EPHY1   28
0059
0060 /* GPIO control registers */
0061 #define AR7_GPIO_INPUT  0x0
0062 #define AR7_GPIO_OUTPUT 0x4
0063 #define AR7_GPIO_DIR    0x8
0064 #define AR7_GPIO_ENABLE 0xc
0065 #define TITAN_GPIO_INPUT_0  0x0
0066 #define TITAN_GPIO_INPUT_1  0x4
0067 #define TITAN_GPIO_OUTPUT_0 0x8
0068 #define TITAN_GPIO_OUTPUT_1 0xc
0069 #define TITAN_GPIO_DIR_0    0x10
0070 #define TITAN_GPIO_DIR_1    0x14
0071 #define TITAN_GPIO_ENBL_0   0x18
0072 #define TITAN_GPIO_ENBL_1   0x1c
0073
0074 #define AR7_CHIP_7100   0x18
0075 #define AR7_CHIP_7200   0x2b
0076 #define AR7_CHIP_7300   0x05
0077 #define AR7_CHIP_TITAN  0x07
0078 #define TITAN_CHIP_1050 0x0f
0079 #define TITAN_CHIP_1055 0x0e
0080 #define TITAN_CHIP_1056 0x0d
0081 #define TITAN_CHIP_1060 0x07
0082
0083 /* Interrupts */
0084 #define AR7_IRQ_UART0   15
0085 #define AR7_IRQ_UART1   16
0086
0087 /* Clocks */
0088 #define AR7_AFE_CLOCK   35328000
0089 #define AR7_REF_CLOCK   25000000
0090 #define AR7_XTAL_CLOCK  24000000
0091
0092 /* DCL */
0093 #define AR7_WDT_HW_ENA  0x10
0094
0095 struct plat_cpmac_data {
0096     int reset_bit;
0097     int power_bit;
0098     u32 phy_mask;
0099     char dev_addr[6];
0100 };
0101
0102 struct plat_dsl_data {
0103     int reset_bit_dsl;
0104     int reset_bit_sar;
0105 };
0106
0107 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
0108
0109 static inline int ar7_is_titan(void)
0110 {
0111     return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
0112         AR7_CHIP_TITAN;
0113 }
0114
0115 static inline u16 ar7_chip_id(void)
0116 {
0117     return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
0118         KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
0119 }
0120
0121 static inline u16 titan_chip_id(void)
0122 {
0123     unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
0124                         TITAN_GPIO_INPUT_1));
0125     return ((val >> 12) & 0x0f);
0126 }
0127
0128 static inline u8 ar7_chip_rev(void)
0129 {
0130     return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
0131         0x14))) >> 16) & 0xff;
0132 }
0133
0134 static inline int ar7_has_high_cpmac(void)
0135 {
0136     u16 chip_id = ar7_chip_id();
0137     switch (chip_id) {
0138     case AR7_CHIP_7100:
0139     case AR7_CHIP_7200:
0140         return 0;
0141     case AR7_CHIP_7300:
0142         return 1;
0143     default:
0144         return -ENXIO;
0145     }
0146 }
0147 #define ar7_has_high_vlynq ar7_has_high_cpmac
0148 #define ar7_has_second_uart ar7_has_high_cpmac
0149
0150 static inline void ar7_device_enable(u32 bit)
0151 {
0152     void *reset_reg =
0153         (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
0154     writel(readl(reset_reg) | (1 << bit), reset_reg);
0155     msleep(20);
0156 }
0157
0158 static inline void ar7_device_disable(u32 bit)
0159 {
0160     void *reset_reg =
0161         (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
0162     writel(readl(reset_reg) & ~(1 << bit), reset_reg);
0163     msleep(20);
0164 }
0165
0166 static inline void ar7_device_reset(u32 bit)
0167 {
0168     ar7_device_disable(bit);
0169     ar7_device_enable(bit);
0170 }
0171
0172 static inline void ar7_device_on(u32 bit)
0173 {
0174     void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
0175     writel(readl(power_reg) | (1 << bit), power_reg);
0176     msleep(20);
0177 }
0178
0179 static inline void ar7_device_off(u32 bit)
0180 {
0181     void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
0182     writel(readl(power_reg) & ~(1 << bit), power_reg);
0183     msleep(20);
0184 }
0185
0186 int __init ar7_gpio_init(void);
0187 void __init ar7_init_clocks(void);
0188
0189 /* Board specific GPIO functions */
0190 int ar7_gpio_enable(unsigned gpio);
0191 int ar7_gpio_disable(unsigned gpio);
0192
0193 #endif /* __AR7_H__ */