include/asm/jazzdma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
0004  */
0005 #ifndef _ASM_JAZZDMA_H
0006 #define _ASM_JAZZDMA_H
0007
0008 /*
0009  * Prototypes and macros
0010  */
0011 extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
0012 extern int vdma_free(unsigned long laddr);
0013 extern unsigned long vdma_phys2log(unsigned long paddr);
0014 extern unsigned long vdma_log2phys(unsigned long laddr);
0015 extern void vdma_stats(void);       /* for debugging only */
0016
0017 extern void vdma_enable(int channel);
0018 extern void vdma_disable(int channel);
0019 extern void vdma_set_mode(int channel, int mode);
0020 extern void vdma_set_addr(int channel, long addr);
0021 extern void vdma_set_count(int channel, int count);
0022 extern int vdma_get_residue(int channel);
0023 extern int vdma_get_enable(int channel);
0024
0025 /*
0026  * some definitions used by the driver functions
0027  */
0028 #define VDMA_PAGESIZE       4096
0029 #define VDMA_PGTBL_ENTRIES  4096
0030 #define VDMA_PGTBL_SIZE     (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
0031 #define VDMA_PAGE_EMPTY     0xff000000
0032
0033 /*
0034  * Macros to get page no. and offset of a given address
0035  * Note that VDMA_PAGE() works for physical addresses only
0036  */
0037 #define VDMA_PAGE(a)        ((unsigned int)(a) >> 12)
0038 #define VDMA_OFFSET(a)      ((unsigned int)(a) & (VDMA_PAGESIZE-1))
0039
0040 /*
0041  * VDMA pagetable entry description
0042  */
0043 typedef volatile struct VDMA_PGTBL_ENTRY {
0044     unsigned int frame;     /* physical frame no. */
0045     unsigned int owner;     /* owner of this entry (0=free) */
0046 } VDMA_PGTBL_ENTRY;
0047
0048
0049 /*
0050  * DMA channel control registers
0051  * in the R4030 MCT_ADR chip
0052  */
0053 #define JAZZ_R4030_CHNL_MODE    0xE0000100  /* 8 DMA Channel Mode Registers, */
0054                         /* 0xE0000100,120,140... */
0055 #define JAZZ_R4030_CHNL_ENABLE  0xE0000108  /* 8 DMA Channel Enable Regs, */
0056                         /* 0xE0000108,128,148... */
0057 #define JAZZ_R4030_CHNL_COUNT   0xE0000110  /* 8 DMA Channel Byte Cnt Regs, */
0058                         /* 0xE0000110,130,150... */
0059 #define JAZZ_R4030_CHNL_ADDR    0xE0000118  /* 8 DMA Channel Address Regs, */
0060                         /* 0xE0000118,138,158... */
0061
0062 /* channel enable register bits */
0063
0064 #define R4030_CHNL_ENABLE    (1<<0)
0065 #define R4030_CHNL_WRITE     (1<<1)
0066 #define R4030_TC_INTR        (1<<8)
0067 #define R4030_MEM_INTR       (1<<9)
0068 #define R4030_ADDR_INTR      (1<<10)
0069
0070 /*
0071  * Channel mode register bits
0072  */
0073 #define R4030_MODE_ATIME_40  (0) /* device access time on remote bus */
0074 #define R4030_MODE_ATIME_80  (1)
0075 #define R4030_MODE_ATIME_120     (2)
0076 #define R4030_MODE_ATIME_160     (3)
0077 #define R4030_MODE_ATIME_200     (4)
0078 #define R4030_MODE_ATIME_240     (5)
0079 #define R4030_MODE_ATIME_280     (6)
0080 #define R4030_MODE_ATIME_320     (7)
0081 #define R4030_MODE_WIDTH_8   (1<<3) /* device data bus width */
0082 #define R4030_MODE_WIDTH_16  (2<<3)
0083 #define R4030_MODE_WIDTH_32  (3<<3)
0084 #define R4030_MODE_INTR_EN   (1<<5)
0085 #define R4030_MODE_BURST     (1<<6) /* Rev. 2 only */
0086 #define R4030_MODE_FAST_ACK  (1<<7) /* Rev. 2 only */
0087
0088 #endif /* _ASM_JAZZDMA_H */