include/asm/jazz.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
0007  */
0008 #ifndef __ASM_JAZZ_H
0009 #define __ASM_JAZZ_H
0010
0011 /*
0012  * The addresses below are virtual address. The mappings are
0013  * created on startup via wired entries in the tlb. The Mips
0014  * Magnum R3000 and R4000 machines are similar in many aspects,
0015  * but many hardware register are accessible at 0xb9000000 in
0016  * instead of 0xe0000000.
0017  */
0018
0019 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
0020
0021 /*
0022  * Revision numbers in PICA_ASIC_REVISION
0023  *
0024  * 0xf0000000 - Rev1
0025  * 0xf0000001 - Rev2
0026  * 0xf0000002 - Rev3
0027  */
0028 #define PICA_ASIC_REVISION  0xe0000008
0029
0030 /*
0031  * The segments of the seven segment LED are mapped
0032  * to the control bits as follows:
0033  *
0034  *     (7)
0035  *  ---------
0036  *  |   |
0037  *  (2) |   | (6)
0038  *  |  (1)  |
0039  *  ---------
0040  *  |   |
0041  *  (3) |   | (5)
0042  *  |  (4)  |
0043  *  --------- . (0)
0044  */
0045 #define PICA_LED        0xe000f000
0046
0047 /*
0048  * Some characters for the LED control registers
0049  * The original Mips machines seem to have a LED display
0050  * with integrated decoder while the Acer machines can
0051  * control each of the seven segments and the dot independently.
0052  * It's only a toy, anyway...
0053  */
0054 #define LED_DOT         0x01
0055 #define LED_SPACE       0x00
0056 #define LED_0           0xfc
0057 #define LED_1           0x60
0058 #define LED_2           0xda
0059 #define LED_3           0xf2
0060 #define LED_4           0x66
0061 #define LED_5           0xb6
0062 #define LED_6           0xbe
0063 #define LED_7           0xe0
0064 #define LED_8           0xfe
0065 #define LED_9           0xf6
0066 #define LED_A           0xee
0067 #define LED_b           0x3e
0068 #define LED_C           0x9c
0069 #define LED_d           0x7a
0070 #define LED_E           0x9e
0071 #define LED_F           0x8e
0072
0073 #ifndef __ASSEMBLY__
0074
0075 static __inline__ void pica_set_led(unsigned int bits)
0076 {
0077     volatile unsigned int *led_register = (unsigned int *) PICA_LED;
0078
0079     *led_register = bits;
0080 }
0081
0082 #endif /* !__ASSEMBLY__ */
0083
0084 /*
0085  * Base address of the Sonic Ethernet adapter in Jazz machines.
0086  */
0087 #define JAZZ_ETHERNET_BASE  0xe0001000
0088
0089 /*
0090  * Base address of the 53C94 SCSI hostadapter in Jazz machines.
0091  */
0092 #define JAZZ_SCSI_BASE      0xe0002000
0093
0094 /*
0095  * i8042 keyboard controller for JAZZ and PICA chipsets.
0096  * This address is just a guess and seems to differ from
0097  * other mips machines such as RC3xxx...
0098  */
0099 #define JAZZ_KEYBOARD_ADDRESS   0xe0005000
0100 #define JAZZ_KEYBOARD_DATA  0xe0005000
0101 #define JAZZ_KEYBOARD_COMMAND   0xe0005001
0102
0103 #ifndef __ASSEMBLY__
0104
0105 typedef struct {
0106     unsigned char data;
0107     unsigned char command;
0108 } jazz_keyboard_hardware;
0109
0110 #define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
0111
0112 typedef struct {
0113     unsigned char pad0[3];
0114     unsigned char data;
0115     unsigned char pad1[3];
0116     unsigned char command;
0117 } mips_keyboard_hardware;
0118
0119 /*
0120  * For now. Needs to be changed for RC3xxx support. See below.
0121  */
0122 #define keyboard_hardware   jazz_keyboard_hardware
0123
0124 #endif /* !__ASSEMBLY__ */
0125
0126 /*
0127  * i8042 keyboard controller for most other Mips machines.
0128  */
0129 #define MIPS_KEYBOARD_ADDRESS   0xb9005000
0130 #define MIPS_KEYBOARD_DATA  0xb9005003
0131 #define MIPS_KEYBOARD_COMMAND   0xb9005007
0132
0133 /*
0134  * Serial and parallel ports (WD 16C552) on the Mips JAZZ
0135  */
0136 #define JAZZ_SERIAL1_BASE   (unsigned int)0xe0006000
0137 #define JAZZ_SERIAL2_BASE   (unsigned int)0xe0007000
0138 #define JAZZ_PARALLEL_BASE  (unsigned int)0xe0008000
0139
0140 /*
0141  * Dummy Device Address. Used in jazzdma.c
0142  */
0143 #define JAZZ_DUMMY_DEVICE   0xe000d000
0144
0145 /*
0146  * JAZZ timer registers and interrupt no.
0147  * Note that the hardware timer interrupt is actually on
0148  * cpu level 6, but to keep compatibility with PC stuff
0149  * it is remapped to vector 0. See arch/mips/kernel/entry.S.
0150  */
0151 #define JAZZ_TIMER_INTERVAL 0xe0000228
0152 #define JAZZ_TIMER_REGISTER 0xe0000230
0153
0154 /*
0155  * DRAM configuration register
0156  */
0157 #ifndef __ASSEMBLY__
0158 #ifdef __MIPSEL__
0159 typedef struct {
0160     unsigned int bank2 : 3;
0161     unsigned int bank1 : 3;
0162     unsigned int mem_bus_width : 1;
0163     unsigned int reserved2 : 1;
0164     unsigned int page_mode : 1;
0165     unsigned int reserved1 : 23;
0166 } dram_configuration;
0167 #else /* defined (__MIPSEB__) */
0168 typedef struct {
0169     unsigned int reserved1 : 23;
0170     unsigned int page_mode : 1;
0171     unsigned int reserved2 : 1;
0172     unsigned int mem_bus_width : 1;
0173     unsigned int bank1 : 3;
0174     unsigned int bank2 : 3;
0175 } dram_configuration;
0176 #endif
0177 #endif /* !__ASSEMBLY__ */
0178
0179 #define PICA_DRAM_CONFIG    0xe00fffe0
0180
0181 /*
0182  * JAZZ interrupt control registers
0183  */
0184 #define JAZZ_IO_IRQ_SOURCE  0xe0010000
0185 #define JAZZ_IO_IRQ_ENABLE  0xe0010002
0186
0187 /*
0188  * JAZZ Interrupt Level definitions
0189  *
0190  * This is somewhat broken.  For reasons which nobody can remember anymore
0191  * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
0192  */
0193 #define JAZZ_IRQ_START      24
0194 #define JAZZ_IRQ_END        (24 + 9)
0195 #define JAZZ_PARALLEL_IRQ   (JAZZ_IRQ_START + 0)
0196 #define JAZZ_FLOPPY_IRQ     (JAZZ_IRQ_START + 1)
0197 #define JAZZ_SOUND_IRQ      (JAZZ_IRQ_START + 2)
0198 #define JAZZ_VIDEO_IRQ      (JAZZ_IRQ_START + 3)
0199 #define JAZZ_ETHERNET_IRQ   (JAZZ_IRQ_START + 4)
0200 #define JAZZ_SCSI_IRQ       (JAZZ_IRQ_START + 5)
0201 #define JAZZ_KEYBOARD_IRQ   (JAZZ_IRQ_START + 6)
0202 #define JAZZ_MOUSE_IRQ      (JAZZ_IRQ_START + 7)
0203 #define JAZZ_SERIAL1_IRQ    (JAZZ_IRQ_START + 8)
0204 #define JAZZ_SERIAL2_IRQ    (JAZZ_IRQ_START + 9)
0205
0206 #define JAZZ_TIMER_IRQ      (MIPS_CPU_IRQ_BASE+6)
0207
0208
0209 /*
0210  * JAZZ DMA Channels
0211  * Note: Channels 4...7 are not used with respect to the Acer PICA-61
0212  * chipset which does not provide these DMA channels.
0213  */
0214 #define JAZZ_SCSI_DMA       0          /* SCSI */
0215 #define JAZZ_FLOPPY_DMA     1          /* FLOPPY */
0216 #define JAZZ_AUDIOL_DMA     2          /* AUDIO L */
0217 #define JAZZ_AUDIOR_DMA     3          /* AUDIO R */
0218
0219 /*
0220  * JAZZ R4030 MCT_ADR chip (DMA controller)
0221  * Note: Virtual Addresses !
0222  */
0223 #define JAZZ_R4030_CONFIG   0xE0000000  /* R4030 config register */
0224 #define JAZZ_R4030_REVISION 0xE0000008  /* same as PICA_ASIC_REVISION */
0225 #define JAZZ_R4030_INV_ADDR 0xE0000010  /* Invalid Address register */
0226
0227 #define JAZZ_R4030_TRSTBL_BASE  0xE0000018  /* Translation Table Base */
0228 #define JAZZ_R4030_TRSTBL_LIM   0xE0000020  /* Translation Table Limit */
0229 #define JAZZ_R4030_TRSTBL_INV   0xE0000028  /* Translation Table Invalidate */
0230
0231 #define JAZZ_R4030_CACHE_MTNC   0xE0000030  /* Cache Maintenance */
0232 #define JAZZ_R4030_R_FAIL_ADDR  0xE0000038  /* Remote Failed Address */
0233 #define JAZZ_R4030_M_FAIL_ADDR  0xE0000040  /* Memory Failed Address */
0234
0235 #define JAZZ_R4030_CACHE_PTAG   0xE0000048  /* I/O Cache Physical Tag */
0236 #define JAZZ_R4030_CACHE_LTAG   0xE0000050  /* I/O Cache Logical Tag */
0237 #define JAZZ_R4030_CACHE_BMASK  0xE0000058  /* I/O Cache Byte Mask */
0238 #define JAZZ_R4030_CACHE_BWIN   0xE0000060  /* I/O Cache Buffer Window */
0239
0240 /*
0241  * Remote Speed Registers.
0242  *
0243  *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
0244  *  4: RTC,   5: Kb./Mouse  6: serial 1,  7: serial 2,
0245  *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
0246  * 12: reserved, 13: free,     14: 7seg LED, 15: ???
0247  */
0248 #define JAZZ_R4030_REM_SPEED    0xE0000070  /* 16 Remote Speed Registers */
0249                         /* 0xE0000070,78,80... 0xE00000E8 */
0250 #define JAZZ_R4030_IRQ_ENABLE   0xE00000E8  /* Internal Interrupt Enable */
0251 #define JAZZ_R4030_INVAL_ADDR   0xE0000010  /* Invalid address Register */
0252 #define JAZZ_R4030_IRQ_SOURCE   0xE0000200  /* Interrupt Source Register */
0253 #define JAZZ_R4030_I386_ERROR   0xE0000208  /* i386/EISA Bus Error */
0254
0255 /*
0256  * Virtual (E)ISA controller address
0257  */
0258 #define JAZZ_EISA_IRQ_ACK   0xE0000238  /* EISA interrupt acknowledge */
0259
0260 /*
0261  * Access the R4030 DMA and I/O Controller
0262  */
0263 #ifndef __ASSEMBLY__
0264
0265 static inline void r4030_delay(void)
0266 {
0267 __asm__ __volatile__(
0268     ".set\tnoreorder\n\t"
0269     "nop\n\t"
0270     "nop\n\t"
0271     "nop\n\t"
0272     "nop\n\t"
0273     ".set\treorder");
0274 }
0275
0276 static inline unsigned short r4030_read_reg16(unsigned long addr)
0277 {
0278     unsigned short ret = *((volatile unsigned short *)addr);
0279     r4030_delay();
0280     return ret;
0281 }
0282
0283 static inline unsigned int r4030_read_reg32(unsigned long addr)
0284 {
0285     unsigned int ret = *((volatile unsigned int *)addr);
0286     r4030_delay();
0287     return ret;
0288 }
0289
0290 static inline void r4030_write_reg16(unsigned long addr, unsigned val)
0291 {
0292     *((volatile unsigned short *)addr) = val;
0293     r4030_delay();
0294 }
0295
0296 static inline void r4030_write_reg32(unsigned long addr, unsigned val)
0297 {
0298     *((volatile unsigned int *)addr) = val;
0299     r4030_delay();
0300 }
0301
0302 #endif /* !__ASSEMBLY__ */
0303
0304 #define JAZZ_FDC_BASE   0xe0003000
0305 #define JAZZ_RTC_BASE   0xe0004000
0306 #define JAZZ_PORT_BASE  0xe2000000
0307
0308 #define JAZZ_EISA_BASE  0xe3000000
0309
0310 #endif /* __ASM_JAZZ_H */