asm/ip32/mace.h

0001 /*
0002  * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 2000 Harald Koerfgen
0009  * Copyright (C) 2004 Ladislav Michl
0010  */
0011
0012 #ifndef __ASM_MACE_H__
0013 #define __ASM_MACE_H__
0014
0015 /*
0016  * Address map
0017  */
0018 #define MACE_BASE   0x1f000000  /* physical */
0019
0020 /*
0021  * PCI interface
0022  */
0023 struct mace_pci {
0024     volatile unsigned int error_addr;
0025     volatile unsigned int error;
0026 #define MACEPCI_ERROR_MASTER_ABORT      BIT(31)
0027 #define MACEPCI_ERROR_TARGET_ABORT      BIT(30)
0028 #define MACEPCI_ERROR_DATA_PARITY_ERR       BIT(29)
0029 #define MACEPCI_ERROR_RETRY_ERR         BIT(28)
0030 #define MACEPCI_ERROR_ILLEGAL_CMD       BIT(27)
0031 #define MACEPCI_ERROR_SYSTEM_ERR        BIT(26)
0032 #define MACEPCI_ERROR_INTERRUPT_TEST        BIT(25)
0033 #define MACEPCI_ERROR_PARITY_ERR        BIT(24)
0034 #define MACEPCI_ERROR_OVERRUN           BIT(23)
0035 #define MACEPCI_ERROR_RSVD          BIT(22)
0036 #define MACEPCI_ERROR_MEMORY_ADDR       BIT(21)
0037 #define MACEPCI_ERROR_CONFIG_ADDR       BIT(20)
0038 #define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
0039 #define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
0040 #define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
0041 #define MACEPCI_ERROR_RETRY_ADDR_VALID      BIT(16)
0042 #define MACEPCI_ERROR_SIG_TABORT        BIT(4)
0043 #define MACEPCI_ERROR_DEVSEL_MASK       0xc0
0044 #define MACEPCI_ERROR_DEVSEL_FAST       0
0045 #define MACEPCI_ERROR_DEVSEL_MED        0x40
0046 #define MACEPCI_ERROR_DEVSEL_SLOW       0x80
0047 #define MACEPCI_ERROR_FBB           BIT(1)
0048 #define MACEPCI_ERROR_66MHZ         BIT(0)
0049     volatile unsigned int control;
0050 #define MACEPCI_CONTROL_INT(x)          BIT(x)
0051 #define MACEPCI_CONTROL_INT_MASK        0xff
0052 #define MACEPCI_CONTROL_SERR_ENA        BIT(8)
0053 #define MACEPCI_CONTROL_ARB_N6          BIT(9)
0054 #define MACEPCI_CONTROL_PARITY_ERR      BIT(10)
0055 #define MACEPCI_CONTROL_MRMRA_ENA       BIT(11)
0056 #define MACEPCI_CONTROL_ARB_N3          BIT(12)
0057 #define MACEPCI_CONTROL_ARB_N4          BIT(13)
0058 #define MACEPCI_CONTROL_ARB_N5          BIT(14)
0059 #define MACEPCI_CONTROL_PARK_LIU        BIT(15)
0060 #define MACEPCI_CONTROL_INV_INT(x)      BIT(16+x)
0061 #define MACEPCI_CONTROL_INV_INT_MASK        0x00ff0000
0062 #define MACEPCI_CONTROL_OVERRUN_INT     BIT(24)
0063 #define MACEPCI_CONTROL_PARITY_INT      BIT(25)
0064 #define MACEPCI_CONTROL_SERR_INT        BIT(26)
0065 #define MACEPCI_CONTROL_IT_INT          BIT(27)
0066 #define MACEPCI_CONTROL_RE_INT          BIT(28)
0067 #define MACEPCI_CONTROL_DPED_INT        BIT(29)
0068 #define MACEPCI_CONTROL_TAR_INT         BIT(30)
0069 #define MACEPCI_CONTROL_MAR_INT         BIT(31)
0070     volatile unsigned int rev;
0071     unsigned int _pad[0xcf8/4 - 4];
0072     volatile unsigned int config_addr;
0073     union {
0074         volatile unsigned char b[4];
0075         volatile unsigned short w[2];
0076         volatile unsigned int l;
0077     } config_data;
0078 };
0079 #define MACEPCI_LOW_MEMORY      0x1a000000
0080 #define MACEPCI_LOW_IO          0x18000000
0081 #define MACEPCI_SWAPPED_VIEW        0
0082 #define MACEPCI_NATIVE_VIEW     0x40000000
0083 #define MACEPCI_IO          0x80000000
0084 #define MACEPCI_HI_MEMORY       0x280000000
0085 #define MACEPCI_HI_IO           0x100000000
0086
0087 /*
0088  * Video interface
0089  */
0090 struct mace_video {
0091     unsigned long xxx;  /* later... */
0092 };
0093
0094 /*
0095  * Ethernet interface
0096  */
0097 struct mace_ethernet {
0098     volatile u64 mac_ctrl;
0099     volatile unsigned long int_stat;
0100     volatile unsigned long dma_ctrl;
0101     volatile unsigned long timer;
0102     volatile unsigned long tx_int_al;
0103     volatile unsigned long rx_int_al;
0104     volatile unsigned long tx_info;
0105     volatile unsigned long tx_info_al;
0106     volatile unsigned long rx_buff;
0107     volatile unsigned long rx_buff_al1;
0108     volatile unsigned long rx_buff_al2;
0109     volatile unsigned long diag;
0110     volatile unsigned long phy_data;
0111     volatile unsigned long phy_regs;
0112     volatile unsigned long phy_trans_go;
0113     volatile unsigned long backoff_seed;
0114     /*===================================*/
0115     volatile unsigned long imq_reserved[4];
0116     volatile unsigned long mac_addr;
0117     volatile unsigned long mac_addr2;
0118     volatile unsigned long mcast_filter;
0119     volatile unsigned long tx_ring_base;
0120     /* Following are read-only registers for debugging */
0121     volatile unsigned long tx_pkt1_hdr;
0122     volatile unsigned long tx_pkt1_ptr[3];
0123     volatile unsigned long tx_pkt2_hdr;
0124     volatile unsigned long tx_pkt2_ptr[3];
0125     /*===================================*/
0126     volatile unsigned long rx_fifo;
0127 };
0128
0129 /*
0130  * Peripherals
0131  */
0132
0133 /* Audio registers */
0134 struct mace_audio {
0135     volatile unsigned long control;
0136     volatile unsigned long codec_control;       /* codec status control */
0137     volatile unsigned long codec_mask;      /* codec status input mask */
0138     volatile unsigned long codec_read;      /* codec status read data */
0139     struct {
0140         volatile unsigned long control;     /* channel control */
0141         volatile unsigned long read_ptr;    /* channel read pointer */
0142         volatile unsigned long write_ptr;   /* channel write pointer */
0143         volatile unsigned long depth;       /* channel depth */
0144     } chan[3];
0145 };
0146
0147
0148 /* register definitions for parallel port DMA */
0149 struct mace_parport {
0150     /* 0 - do nothing,
0151      * 1 - pulse terminal count to the device after buffer is drained */
0152 #define MACEPAR_CONTEXT_LASTFLAG    BIT(63)
0153     /* Should not cross 4K page boundary */
0154 #define MACEPAR_CONTEXT_DATA_BOUND  0x0000000000001000UL
0155 #define MACEPAR_CONTEXT_DATALEN_MASK    0x00000fff00000000UL
0156 #define MACEPAR_CONTEXT_DATALEN_SHIFT   32
0157     /* Can be arbitrarily aligned on any byte boundary on output,
0158      * 64 byte aligned on input */
0159 #define MACEPAR_CONTEXT_BASEADDR_MASK   0x00000000ffffffffUL
0160     volatile u64 context_a;
0161     volatile u64 context_b;
0162     /* 0 - mem->device, 1 - device->mem */
0163 #define MACEPAR_CTLSTAT_DIRECTION   BIT(0)
0164     /* 0 - channel frozen, 1 - channel enabled */
0165 #define MACEPAR_CTLSTAT_ENABLE      BIT(1)
0166     /* 0 - channel active, 1 - complete channel reset */
0167 #define MACEPAR_CTLSTAT_RESET       BIT(2)
0168 #define MACEPAR_CTLSTAT_CTXB_VALID  BIT(3)
0169 #define MACEPAR_CTLSTAT_CTXA_VALID  BIT(4)
0170     volatile u64 cntlstat;      /* Control/Status register */
0171 #define MACEPAR_DIAG_CTXINUSE       BIT(0)
0172     /* 1 - Dma engine is enabled and processing something */
0173 #define MACEPAR_DIAG_DMACTIVE       BIT(1)
0174     /* Counter of bytes left */
0175 #define MACEPAR_DIAG_CTRMASK        0x0000000000003ffcUL
0176 #define MACEPAR_DIAG_CTRSHIFT       2
0177     volatile u64 diagnostic;    /* RO: diagnostic register */
0178 };
0179
0180 /* ISA Control and DMA registers */
0181 struct mace_isactrl {
0182     volatile unsigned long ringbase;
0183 #define MACEISA_RINGBUFFERS_SIZE    (8 * 4096)
0184
0185     volatile unsigned long misc;
0186 #define MACEISA_FLASH_WE        BIT(0)  /* 1=> Enable FLASH writes */
0187 #define MACEISA_PWD_CLEAR       BIT(1)  /* 1=> PWD CLEAR jumper detected */
0188 #define MACEISA_NIC_DEASSERT        BIT(2)
0189 #define MACEISA_NIC_DATA        BIT(3)
0190 #define MACEISA_LED_RED         BIT(4)  /* 0=> Illuminate red LED */
0191 #define MACEISA_LED_GREEN       BIT(5)  /* 0=> Illuminate green LED */
0192 #define MACEISA_DP_RAM_ENABLE       BIT(6)
0193
0194     volatile unsigned long istat;
0195     volatile unsigned long imask;
0196 #define MACEISA_AUDIO_SW_INT        BIT(0)
0197 #define MACEISA_AUDIO_SC_INT        BIT(1)
0198 #define MACEISA_AUDIO1_DMAT_INT     BIT(2)
0199 #define MACEISA_AUDIO1_OF_INT       BIT(3)
0200 #define MACEISA_AUDIO2_DMAT_INT     BIT(4)
0201 #define MACEISA_AUDIO2_MERR_INT     BIT(5)
0202 #define MACEISA_AUDIO3_DMAT_INT     BIT(6)
0203 #define MACEISA_AUDIO3_MERR_INT     BIT(7)
0204 #define MACEISA_RTC_INT         BIT(8)
0205 #define MACEISA_KEYB_INT        BIT(9)
0206 #define MACEISA_KEYB_POLL_INT       BIT(10)
0207 #define MACEISA_MOUSE_INT       BIT(11)
0208 #define MACEISA_MOUSE_POLL_INT      BIT(12)
0209 #define MACEISA_TIMER0_INT      BIT(13)
0210 #define MACEISA_TIMER1_INT      BIT(14)
0211 #define MACEISA_TIMER2_INT      BIT(15)
0212 #define MACEISA_PARALLEL_INT        BIT(16)
0213 #define MACEISA_PAR_CTXA_INT        BIT(17)
0214 #define MACEISA_PAR_CTXB_INT        BIT(18)
0215 #define MACEISA_PAR_MERR_INT        BIT(19)
0216 #define MACEISA_SERIAL1_INT     BIT(20)
0217 #define MACEISA_SERIAL1_TDMAT_INT   BIT(21)
0218 #define MACEISA_SERIAL1_TDMAPR_INT  BIT(22)
0219 #define MACEISA_SERIAL1_TDMAME_INT  BIT(23)
0220 #define MACEISA_SERIAL1_RDMAT_INT   BIT(24)
0221 #define MACEISA_SERIAL1_RDMAOR_INT  BIT(25)
0222 #define MACEISA_SERIAL2_INT     BIT(26)
0223 #define MACEISA_SERIAL2_TDMAT_INT   BIT(27)
0224 #define MACEISA_SERIAL2_TDMAPR_INT  BIT(28)
0225 #define MACEISA_SERIAL2_TDMAME_INT  BIT(29)
0226 #define MACEISA_SERIAL2_RDMAT_INT   BIT(30)
0227 #define MACEISA_SERIAL2_RDMAOR_INT  BIT(31)
0228
0229     volatile unsigned long _pad[0x2000/8 - 4];
0230
0231     volatile unsigned long dp_ram[0x400];
0232     struct mace_parport parport;
0233 };
0234
0235 /* Keyboard & Mouse registers
0236  * -> drivers/input/serio/maceps2.c */
0237 struct mace_ps2port {
0238     volatile unsigned long tx;
0239     volatile unsigned long rx;
0240     volatile unsigned long control;
0241     volatile unsigned long status;
0242 };
0243
0244 struct mace_ps2 {
0245     struct mace_ps2port keyb;
0246     struct mace_ps2port mouse;
0247 };
0248
0249 /* I2C registers
0250  * -> drivers/i2c/algos/i2c-algo-sgi.c */
0251 struct mace_i2c {
0252     volatile unsigned long config;
0253 #define MACEI2C_RESET       BIT(0)
0254 #define MACEI2C_FAST        BIT(1)
0255 #define MACEI2C_DATA_OVERRIDE   BIT(2)
0256 #define MACEI2C_CLOCK_OVERRIDE  BIT(3)
0257 #define MACEI2C_DATA_STATUS BIT(4)
0258 #define MACEI2C_CLOCK_STATUS    BIT(5)
0259     volatile unsigned long control;
0260     volatile unsigned long data;
0261 };
0262
0263 /* Timer registers */
0264 typedef union {
0265     volatile unsigned long ust_msc;
0266     struct reg {
0267         volatile unsigned int ust;
0268         volatile unsigned int msc;
0269     } reg;
0270 } timer_reg;
0271
0272 struct mace_timers {
0273     volatile unsigned long ust;
0274 #define MACE_UST_PERIOD_NS  960
0275
0276     volatile unsigned long compare1;
0277     volatile unsigned long compare2;
0278     volatile unsigned long compare3;
0279
0280     timer_reg audio_in;
0281     timer_reg audio_out1;
0282     timer_reg audio_out2;
0283     timer_reg video_in1;
0284     timer_reg video_in2;
0285     timer_reg video_out;
0286 };
0287
0288 struct mace_perif {
0289     struct mace_audio audio;
0290     char _pad0[0x10000 - sizeof(struct mace_audio)];
0291
0292     struct mace_isactrl ctrl;
0293     char _pad1[0x10000 - sizeof(struct mace_isactrl)];
0294
0295     struct mace_ps2 ps2;
0296     char _pad2[0x10000 - sizeof(struct mace_ps2)];
0297
0298     struct mace_i2c i2c;
0299     char _pad3[0x10000 - sizeof(struct mace_i2c)];
0300
0301     struct mace_timers timers;
0302     char _pad4[0x10000 - sizeof(struct mace_timers)];
0303 };
0304
0305
0306 /*
0307  * ISA peripherals
0308  */
0309
0310 /* Parallel port */
0311 struct mace_parallel {
0312 };
0313
0314 struct mace_ecp1284 {   /* later... */
0315 };
0316
0317 /* Serial port */
0318 struct mace_serial {
0319     volatile unsigned long xxx; /* later... */
0320 };
0321
0322 struct mace_isa {
0323     struct mace_parallel parallel;
0324     char _pad1[0x8000 - sizeof(struct mace_parallel)];
0325
0326     struct mace_ecp1284 ecp1284;
0327     char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
0328
0329     struct mace_serial serial1;
0330     char _pad3[0x8000 - sizeof(struct mace_serial)];
0331
0332     struct mace_serial serial2;
0333     char _pad4[0x8000 - sizeof(struct mace_serial)];
0334
0335     volatile unsigned char rtc[0x10000];
0336 };
0337
0338 struct sgi_mace {
0339     char _reserved[0x80000];
0340
0341     struct mace_pci pci;
0342     char _pad0[0x80000 - sizeof(struct mace_pci)];
0343
0344     struct mace_video video_in1;
0345     char _pad1[0x80000 - sizeof(struct mace_video)];
0346
0347     struct mace_video video_in2;
0348     char _pad2[0x80000 - sizeof(struct mace_video)];
0349
0350     struct mace_video video_out;
0351     char _pad3[0x80000 - sizeof(struct mace_video)];
0352
0353     struct mace_ethernet eth;
0354     char _pad4[0x80000 - sizeof(struct mace_ethernet)];
0355
0356     struct mace_perif perif;
0357     char _pad5[0x80000 - sizeof(struct mace_perif)];
0358
0359     struct mace_isa isa;
0360     char _pad6[0x80000 - sizeof(struct mace_isa)];
0361 };
0362
0363 extern struct sgi_mace __iomem *mace;
0364
0365 #endif /* __ASM_MACE_H__ */