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0010 #ifndef _ASM_MIPS_FTRACE_H
0011 #define _ASM_MIPS_FTRACE_H
0012
0013 #ifdef CONFIG_FUNCTION_TRACER
0014
0015 #define MCOUNT_ADDR ((unsigned long)(_mcount))
0016 #define MCOUNT_INSN_SIZE 4
0017
0018 #ifndef __ASSEMBLY__
0019 extern void _mcount(void);
0020 #define mcount _mcount
0021
0022 #define safe_load(load, src, dst, error) \
0023 do { \
0024 asm volatile ( \
0025 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
0026 " li %[tmp_err], 0\n" \
0027 "2: .insn\n" \
0028 \
0029 ".section .fixup, \"ax\"\n" \
0030 "3: li %[tmp_err], 1\n" \
0031 " j 2b\n" \
0032 ".previous\n" \
0033 \
0034 ".section\t__ex_table,\"a\"\n\t" \
0035 STR(PTR_WD) "\t1b, 3b\n\t" \
0036 ".previous\n" \
0037 \
0038 : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
0039 : [tmp_src] "r" (src) \
0040 : "memory" \
0041 ); \
0042 } while (0)
0043
0044 #define safe_store(store, src, dst, error) \
0045 do { \
0046 asm volatile ( \
0047 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
0048 " li %[tmp_err], 0\n" \
0049 "2: .insn\n" \
0050 \
0051 ".section .fixup, \"ax\"\n" \
0052 "3: li %[tmp_err], 1\n" \
0053 " j 2b\n" \
0054 ".previous\n" \
0055 \
0056 ".section\t__ex_table,\"a\"\n\t"\
0057 STR(PTR_WD) "\t1b, 3b\n\t" \
0058 ".previous\n" \
0059 \
0060 : [tmp_err] "=r" (error) \
0061 : [tmp_dst] "r" (dst), [tmp_src] "r" (src)\
0062 : "memory" \
0063 ); \
0064 } while (0)
0065
0066 #define safe_load_code(dst, src, error) \
0067 safe_load(STR(lw), src, dst, error)
0068 #define safe_store_code(src, dst, error) \
0069 safe_store(STR(sw), src, dst, error)
0070
0071 #define safe_load_stack(dst, src, error) \
0072 safe_load(STR(PTR_L), src, dst, error)
0073
0074 #define safe_store_stack(src, dst, error) \
0075 safe_store(STR(PTR_S), src, dst, error)
0076
0077
0078 #ifdef CONFIG_DYNAMIC_FTRACE
0079 static inline unsigned long ftrace_call_adjust(unsigned long addr)
0080 {
0081 return addr;
0082 }
0083
0084 struct dyn_arch_ftrace {
0085 };
0086
0087 #endif
0088 #endif
0089 #endif
0090 #endif