include/asm/fpu_emulator.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Further private data for which no space exists in mips_fpu_struct.
0005  * This should be subsumed into the mips_fpu_struct structure as
0006  * defined in processor.h as soon as the absurd wired absolute assembler
0007  * offsets become dynamic at compile time.
0008  *
0009  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
0010  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
0011  */
0012 #ifndef _ASM_FPU_EMULATOR_H
0013 #define _ASM_FPU_EMULATOR_H
0014
0015 #include <linux/sched.h>
0016 #include <asm/dsemul.h>
0017 #include <asm/thread_info.h>
0018 #include <asm/inst.h>
0019 #include <asm/local.h>
0020 #include <asm/processor.h>
0021
0022 #ifdef CONFIG_DEBUG_FS
0023
0024 struct mips_fpu_emulator_stats {
0025     unsigned long emulated;
0026     unsigned long loads;
0027     unsigned long stores;
0028     unsigned long branches;
0029     unsigned long cp1ops;
0030     unsigned long cp1xops;
0031     unsigned long errors;
0032     unsigned long ieee754_inexact;
0033     unsigned long ieee754_underflow;
0034     unsigned long ieee754_overflow;
0035     unsigned long ieee754_zerodiv;
0036     unsigned long ieee754_invalidop;
0037     unsigned long ds_emul;
0038
0039     unsigned long abs_s;
0040     unsigned long abs_d;
0041     unsigned long add_s;
0042     unsigned long add_d;
0043     unsigned long bc1eqz;
0044     unsigned long bc1nez;
0045     unsigned long ceil_w_s;
0046     unsigned long ceil_w_d;
0047     unsigned long ceil_l_s;
0048     unsigned long ceil_l_d;
0049     unsigned long class_s;
0050     unsigned long class_d;
0051     unsigned long cmp_af_s;
0052     unsigned long cmp_af_d;
0053     unsigned long cmp_eq_s;
0054     unsigned long cmp_eq_d;
0055     unsigned long cmp_le_s;
0056     unsigned long cmp_le_d;
0057     unsigned long cmp_lt_s;
0058     unsigned long cmp_lt_d;
0059     unsigned long cmp_ne_s;
0060     unsigned long cmp_ne_d;
0061     unsigned long cmp_or_s;
0062     unsigned long cmp_or_d;
0063     unsigned long cmp_ueq_s;
0064     unsigned long cmp_ueq_d;
0065     unsigned long cmp_ule_s;
0066     unsigned long cmp_ule_d;
0067     unsigned long cmp_ult_s;
0068     unsigned long cmp_ult_d;
0069     unsigned long cmp_un_s;
0070     unsigned long cmp_un_d;
0071     unsigned long cmp_une_s;
0072     unsigned long cmp_une_d;
0073     unsigned long cmp_saf_s;
0074     unsigned long cmp_saf_d;
0075     unsigned long cmp_seq_s;
0076     unsigned long cmp_seq_d;
0077     unsigned long cmp_sle_s;
0078     unsigned long cmp_sle_d;
0079     unsigned long cmp_slt_s;
0080     unsigned long cmp_slt_d;
0081     unsigned long cmp_sne_s;
0082     unsigned long cmp_sne_d;
0083     unsigned long cmp_sor_s;
0084     unsigned long cmp_sor_d;
0085     unsigned long cmp_sueq_s;
0086     unsigned long cmp_sueq_d;
0087     unsigned long cmp_sule_s;
0088     unsigned long cmp_sule_d;
0089     unsigned long cmp_sult_s;
0090     unsigned long cmp_sult_d;
0091     unsigned long cmp_sun_s;
0092     unsigned long cmp_sun_d;
0093     unsigned long cmp_sune_s;
0094     unsigned long cmp_sune_d;
0095     unsigned long cvt_d_l;
0096     unsigned long cvt_d_s;
0097     unsigned long cvt_d_w;
0098     unsigned long cvt_l_s;
0099     unsigned long cvt_l_d;
0100     unsigned long cvt_s_d;
0101     unsigned long cvt_s_l;
0102     unsigned long cvt_s_w;
0103     unsigned long cvt_w_s;
0104     unsigned long cvt_w_d;
0105     unsigned long div_s;
0106     unsigned long div_d;
0107     unsigned long floor_w_s;
0108     unsigned long floor_w_d;
0109     unsigned long floor_l_s;
0110     unsigned long floor_l_d;
0111     unsigned long maddf_s;
0112     unsigned long maddf_d;
0113     unsigned long max_s;
0114     unsigned long max_d;
0115     unsigned long maxa_s;
0116     unsigned long maxa_d;
0117     unsigned long min_s;
0118     unsigned long min_d;
0119     unsigned long mina_s;
0120     unsigned long mina_d;
0121     unsigned long mov_s;
0122     unsigned long mov_d;
0123     unsigned long msubf_s;
0124     unsigned long msubf_d;
0125     unsigned long mul_s;
0126     unsigned long mul_d;
0127     unsigned long neg_s;
0128     unsigned long neg_d;
0129     unsigned long recip_s;
0130     unsigned long recip_d;
0131     unsigned long rint_s;
0132     unsigned long rint_d;
0133     unsigned long round_w_s;
0134     unsigned long round_w_d;
0135     unsigned long round_l_s;
0136     unsigned long round_l_d;
0137     unsigned long rsqrt_s;
0138     unsigned long rsqrt_d;
0139     unsigned long sel_s;
0140     unsigned long sel_d;
0141     unsigned long seleqz_s;
0142     unsigned long seleqz_d;
0143     unsigned long selnez_s;
0144     unsigned long selnez_d;
0145     unsigned long sqrt_s;
0146     unsigned long sqrt_d;
0147     unsigned long sub_s;
0148     unsigned long sub_d;
0149     unsigned long trunc_w_s;
0150     unsigned long trunc_w_d;
0151     unsigned long trunc_l_s;
0152     unsigned long trunc_l_d;
0153 };
0154
0155 DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
0156
0157 #define MIPS_FPU_EMU_INC_STATS(M)                   \
0158 do {                                    \
0159     preempt_disable();                      \
0160     __this_cpu_inc(fpuemustats.M);                  \
0161     preempt_enable();                       \
0162 } while (0)
0163
0164 #else
0165 #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
0166 #endif /* CONFIG_DEBUG_FS */
0167
0168 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
0169                     struct mips_fpu_struct *ctx, int has_fpu,
0170                     void __user **fault_addr);
0171 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
0172              struct task_struct *tsk);
0173 int process_fpemu_return(int sig, void __user *fault_addr,
0174              unsigned long fcr31);
0175
0176 /*
0177  * Mask the FCSR Cause bits according to the Enable bits, observing
0178  * that Unimplemented is always enabled.
0179  */
0180 static inline unsigned long mask_fcr31_x(unsigned long fcr31)
0181 {
0182     return fcr31 & (FPU_CSR_UNI_X |
0183             ((fcr31 & FPU_CSR_ALL_E) <<
0184              (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))));
0185 }
0186
0187 #endif /* _ASM_FPU_EMULATOR_H */