include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
0004  * Written by Hennus Bergman, 1992.
0005  * High DMA channel support & info by Hannu Savolainen
0006  * and John Boyd, Nov. 1992.
0007  *
0008  * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
0009  * and can only be used for expansion cards. Onboard DMA controllers, such
0010  * as the R4030 on Jazz boards behave totally different!
0011  */
0012
0013 #ifndef _ASM_DMA_H
0014 #define _ASM_DMA_H
0015
0016 #include <asm/io.h>         /* need byte IO */
0017 #include <linux/spinlock.h>     /* And spinlocks */
0018 #include <linux/delay.h>
0019
0020
0021 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
0022 #define dma_outb    outb_p
0023 #else
0024 #define dma_outb    outb
0025 #endif
0026
0027 #define dma_inb     inb
0028
0029 /*
0030  * NOTES about DMA transfers:
0031  *
0032  *  controller 1: channels 0-3, byte operations, ports 00-1F
0033  *  controller 2: channels 4-7, word operations, ports C0-DF
0034  *
0035  *  - ALL registers are 8 bits only, regardless of transfer size
0036  *  - channel 4 is not used - cascades 1 into 2.
0037  *  - channels 0-3 are byte - addresses/counts are for physical bytes
0038  *  - channels 5-7 are word - addresses/counts are for physical words
0039  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
0040  *  - transfer count loaded to registers is 1 less than actual count
0041  *  - controller 2 offsets are all even (2x offsets for controller 1)
0042  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
0043  *  - page registers for 0-3 use bit 0, represent 64K pages
0044  *
0045  * DMA transfers are limited to the lower 16MB of _physical_ memory.
0046  * Note that addresses loaded into registers must be _physical_ addresses,
0047  * not logical addresses (which may differ if paging is active).
0048  *
0049  *  Address mapping for channels 0-3:
0050  *
0051  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
0052  *    |  ...  |   |  ... |   |  ... |
0053  *    |  ...  |   |  ... |   |  ... |
0054  *    |  ...  |   |  ... |   |  ... |
0055  *   P7  ...  P0  A7 ... A0  A7 ... A0
0056  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
0057  *
0058  *  Address mapping for channels 5-7:
0059  *
0060  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
0061  *    |  ...  |   \   \   ... \  \  \  ... \  \
0062  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
0063  *    |  ...  |     \   \   ... \  \  \  ... \
0064  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
0065  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
0066  *
0067  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
0068  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
0069  * the hardware level, so odd-byte transfers aren't possible).
0070  *
0071  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
0072  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
0073  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
0074  *
0075  */
0076
0077 #ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
0078 #define MAX_DMA_CHANNELS    8
0079 #endif
0080
0081 /*
0082  * The maximum address in KSEG0 that we can perform a DMA transfer to on this
0083  * platform.  This describes only the PC style part of the DMA logic like on
0084  * Deskstations or Acer PICA but not the much more versatile DMA logic used
0085  * for the local devices on Acer PICA or Magnums.
0086  */
0087 #if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
0088 /* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
0089 #define MAX_DMA_ADDRESS     PAGE_OFFSET
0090 #else
0091 #define MAX_DMA_ADDRESS     (PAGE_OFFSET + 0x01000000)
0092 #endif
0093 #define MAX_DMA_PFN     PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
0094
0095 #ifndef MAX_DMA32_PFN
0096 #define MAX_DMA32_PFN       (1UL << (32 - PAGE_SHIFT))
0097 #endif
0098
0099 /* 8237 DMA controllers */
0100 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
0101 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
0102
0103 /* DMA controller registers */
0104 #define DMA1_CMD_REG        0x08    /* command register (w) */
0105 #define DMA1_STAT_REG       0x08    /* status register (r) */
0106 #define DMA1_REQ_REG        0x09    /* request register (w) */
0107 #define DMA1_MASK_REG       0x0A    /* single-channel mask (w) */
0108 #define DMA1_MODE_REG       0x0B    /* mode register (w) */
0109 #define DMA1_CLEAR_FF_REG   0x0C    /* clear pointer flip-flop (w) */
0110 #define DMA1_TEMP_REG       0x0D    /* Temporary Register (r) */
0111 #define DMA1_RESET_REG      0x0D    /* Master Clear (w) */
0112 #define DMA1_CLR_MASK_REG   0x0E    /* Clear Mask */
0113 #define DMA1_MASK_ALL_REG   0x0F    /* all-channels mask (w) */
0114
0115 #define DMA2_CMD_REG        0xD0    /* command register (w) */
0116 #define DMA2_STAT_REG       0xD0    /* status register (r) */
0117 #define DMA2_REQ_REG        0xD2    /* request register (w) */
0118 #define DMA2_MASK_REG       0xD4    /* single-channel mask (w) */
0119 #define DMA2_MODE_REG       0xD6    /* mode register (w) */
0120 #define DMA2_CLEAR_FF_REG   0xD8    /* clear pointer flip-flop (w) */
0121 #define DMA2_TEMP_REG       0xDA    /* Temporary Register (r) */
0122 #define DMA2_RESET_REG      0xDA    /* Master Clear (w) */
0123 #define DMA2_CLR_MASK_REG   0xDC    /* Clear Mask */
0124 #define DMA2_MASK_ALL_REG   0xDE    /* all-channels mask (w) */
0125
0126 #define DMA_ADDR_0      0x00    /* DMA address registers */
0127 #define DMA_ADDR_1      0x02
0128 #define DMA_ADDR_2      0x04
0129 #define DMA_ADDR_3      0x06
0130 #define DMA_ADDR_4      0xC0
0131 #define DMA_ADDR_5      0xC4
0132 #define DMA_ADDR_6      0xC8
0133 #define DMA_ADDR_7      0xCC
0134
0135 #define DMA_CNT_0       0x01    /* DMA count registers */
0136 #define DMA_CNT_1       0x03
0137 #define DMA_CNT_2       0x05
0138 #define DMA_CNT_3       0x07
0139 #define DMA_CNT_4       0xC2
0140 #define DMA_CNT_5       0xC6
0141 #define DMA_CNT_6       0xCA
0142 #define DMA_CNT_7       0xCE
0143
0144 #define DMA_PAGE_0      0x87    /* DMA page registers */
0145 #define DMA_PAGE_1      0x83
0146 #define DMA_PAGE_2      0x81
0147 #define DMA_PAGE_3      0x82
0148 #define DMA_PAGE_5      0x8B
0149 #define DMA_PAGE_6      0x89
0150 #define DMA_PAGE_7      0x8A
0151
0152 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
0153 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
0154 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
0155
0156 #define DMA_AUTOINIT    0x10
0157
0158 extern spinlock_t  dma_spin_lock;
0159
0160 static __inline__ unsigned long claim_dma_lock(void)
0161 {
0162     unsigned long flags;
0163     spin_lock_irqsave(&dma_spin_lock, flags);
0164     return flags;
0165 }
0166
0167 static __inline__ void release_dma_lock(unsigned long flags)
0168 {
0169     spin_unlock_irqrestore(&dma_spin_lock, flags);
0170 }
0171
0172 /* enable/disable a specific DMA channel */
0173 static __inline__ void enable_dma(unsigned int dmanr)
0174 {
0175     if (dmanr<=3)
0176         dma_outb(dmanr,  DMA1_MASK_REG);
0177     else
0178         dma_outb(dmanr & 3,  DMA2_MASK_REG);
0179 }
0180
0181 static __inline__ void disable_dma(unsigned int dmanr)
0182 {
0183     if (dmanr<=3)
0184         dma_outb(dmanr | 4,  DMA1_MASK_REG);
0185     else
0186         dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
0187 }
0188
0189 /* Clear the 'DMA Pointer Flip Flop'.
0190  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
0191  * Use this once to initialize the FF to a known state.
0192  * After that, keep track of it. :-)
0193  * --- In order to do that, the DMA routines below should ---
0194  * --- only be used while holding the DMA lock ! ---
0195  */
0196 static __inline__ void clear_dma_ff(unsigned int dmanr)
0197 {
0198     if (dmanr<=3)
0199         dma_outb(0,  DMA1_CLEAR_FF_REG);
0200     else
0201         dma_outb(0,  DMA2_CLEAR_FF_REG);
0202 }
0203
0204 /* set mode (above) for a specific DMA channel */
0205 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
0206 {
0207     if (dmanr<=3)
0208         dma_outb(mode | dmanr,  DMA1_MODE_REG);
0209     else
0210         dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
0211 }
0212
0213 /* Set only the page register bits of the transfer address.
0214  * This is used for successive transfers when we know the contents of
0215  * the lower 16 bits of the DMA current address register, but a 64k boundary
0216  * may have been crossed.
0217  */
0218 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
0219 {
0220     switch(dmanr) {
0221         case 0:
0222             dma_outb(pagenr, DMA_PAGE_0);
0223             break;
0224         case 1:
0225             dma_outb(pagenr, DMA_PAGE_1);
0226             break;
0227         case 2:
0228             dma_outb(pagenr, DMA_PAGE_2);
0229             break;
0230         case 3:
0231             dma_outb(pagenr, DMA_PAGE_3);
0232             break;
0233         case 5:
0234             dma_outb(pagenr & 0xfe, DMA_PAGE_5);
0235             break;
0236         case 6:
0237             dma_outb(pagenr & 0xfe, DMA_PAGE_6);
0238             break;
0239         case 7:
0240             dma_outb(pagenr & 0xfe, DMA_PAGE_7);
0241             break;
0242     }
0243 }
0244
0245
0246 /* Set transfer address & page bits for specific DMA channel.
0247  * Assumes dma flipflop is clear.
0248  */
0249 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
0250 {
0251     set_dma_page(dmanr, a>>16);
0252     if (dmanr <= 3)  {
0253         dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
0254         dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
0255     }  else  {
0256         dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
0257         dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
0258     }
0259 }
0260
0261
0262 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
0263  * a specific DMA channel.
0264  * You must ensure the parameters are valid.
0265  * NOTE: from a manual: "the number of transfers is one more
0266  * than the initial word count"! This is taken into account.
0267  * Assumes dma flip-flop is clear.
0268  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
0269  */
0270 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
0271 {
0272     count--;
0273     if (dmanr <= 3)  {
0274         dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
0275         dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
0276     } else {
0277         dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
0278         dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
0279     }
0280 }
0281
0282
0283 /* Get DMA residue count. After a DMA transfer, this
0284  * should return zero. Reading this while a DMA transfer is
0285  * still in progress will return unpredictable results.
0286  * If called before the channel has been used, it may return 1.
0287  * Otherwise, it returns the number of _bytes_ left to transfer.
0288  *
0289  * Assumes DMA flip-flop is clear.
0290  */
0291 static __inline__ int get_dma_residue(unsigned int dmanr)
0292 {
0293     unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
0294                      : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
0295
0296     /* using short to get 16-bit wrap around */
0297     unsigned short count;
0298
0299     count = 1 + dma_inb(io_port);
0300     count += dma_inb(io_port) << 8;
0301
0302     return (dmanr<=3)? count : (count<<1);
0303 }
0304
0305
0306 /* These are in kernel/dma.c: */
0307 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
0308 extern void free_dma(unsigned int dmanr);   /* release it again */
0309
0310 #endif /* _ASM_DMA_H */