asm/dec/kn05.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  include/asm-mips/dec/kn05.h
0004  *
0005  *  DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
0006  *  or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
0007  *  KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
0008  *  definitions.
0009  *
0010  *  Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
0011  *
0012  *  WARNING!  All this information is pure guesswork based on the
0013  *  ROM.  It is provided here in hope it will give someone some
0014  *  food for thought.  No documentation for the KN05 nor the KN04
0015  *  module has been located so far.
0016  */
0017 #ifndef __ASM_MIPS_DEC_KN05_H
0018 #define __ASM_MIPS_DEC_KN05_H
0019
0020 #include <asm/dec/ioasic_addrs.h>
0021
0022 /*
0023  * The oncard MB (Memory Buffer) ASIC provides an additional address
0024  * decoder.  Certain address ranges within the "high" 16 slots are
0025  * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
0026  * Others are handled locally.  "Low" slots are always passed.
0027  */
0028 #define KN4K_SLOT_BASE  0x1fc00000
0029
0030 #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
0031 #define KN4K_IOCTL  (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
0032 #define KN4K_ESAR   (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
0033 #define KN4K_LANCE  (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
0034 #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
0035 #define KN4K_MB_EA  (5*IOASIC_SLOT_SIZE)    /* MB error address? */
0036 #define KN4K_MB_EC  (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
0037 #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE)    /* MB control & status */
0038 #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE)    /* unused? */
0039 #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE)    /* unused? */
0040 #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE)   /* unused? */
0041 #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE)   /* unused? */
0042 #define KN4K_SCSI   (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
0043 #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE)   /* unused? */
0044 #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE)   /* unused? */
0045 #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE)   /* unused? */
0046
0047 /*
0048  * MB ASIC interrupt bits.
0049  */
0050 #define KN4K_MB_INR_MB      4   /* ??? */
0051 #define KN4K_MB_INR_MT      3   /* memory, I/O bus read/write errors */
0052 #define KN4K_MB_INR_RES_2   2   /* unused */
0053 #define KN4K_MB_INR_RTC     1   /* RTC */
0054 #define KN4K_MB_INR_TC      0   /* I/O ASIC cascade */
0055
0056 /*
0057  * Bits for the MB interrupt register.
0058  * The register appears read-only.
0059  */
0060 #define KN4K_MB_INT_IRQ     (0x1f<<0)   /* CPU Int[4:0] status. */
0061 #define KN4K_MB_INT_IRQ_N(n)    (1<<(n))    /* Individual status bits. */
0062
0063 /*
0064  * Bits for the MB control & status register.
0065  * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
0066  */
0067 #define KN4K_MB_CSR_PF      (1<<0)      /* PreFetching enable? */
0068 #define KN4K_MB_CSR_F       (1<<1)      /* ??? */
0069 #define KN4K_MB_CSR_ECC     (0xff<<2)   /* ??? */
0070 #define KN4K_MB_CSR_OD      (1<<10)     /* ??? */
0071 #define KN4K_MB_CSR_CP      (1<<11)     /* ??? */
0072 #define KN4K_MB_CSR_UNC     (1<<12)     /* ??? */
0073 #define KN4K_MB_CSR_IM      (1<<13)     /* ??? */
0074 #define KN4K_MB_CSR_NC      (1<<14)     /* ??? */
0075 #define KN4K_MB_CSR_EE      (1<<15)     /* (bus) Exception Enable? */
0076 #define KN4K_MB_CSR_MSK     (0x1f<<16)  /* CPU Int[4:0] mask */
0077 #define KN4K_MB_CSR_MSK_N(n)    (1<<((n)+16))   /* Individual mask bits. */
0078 #define KN4K_MB_CSR_FW      (1<<21)     /* ??? */
0079 #define KN4K_MB_CSR_W       (1<<31)     /* ??? */
0080
0081 #endif /* __ASM_MIPS_DEC_KN05_H */