asm/dec/ioasic_ints.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Definitions for the interrupt related bits in the I/O ASIC
0007  * interrupt status register (and the interrupt mask register, of course)
0008  *
0009  * Created with Information from:
0010  *
0011  * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
0012  *
0013  * and the Mach Sources
0014  *
0015  * Copyright (C) 199x  the Anonymous
0016  * Copyright (C) 2002  Maciej W. Rozycki
0017  */
0018
0019 #ifndef __ASM_DEC_IOASIC_INTS_H
0020 #define __ASM_DEC_IOASIC_INTS_H
0021
0022 /*
0023  * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
0024  * and thus are common to all I/O ASIC machines.  The exception is
0025  * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
0026  * unused) and has a different SCC wiring.
0027  */
0028                     /* all systems */
0029 #define IO_INR_SCC0A_TXDMA  31  /* SCC0A transmit page end */
0030 #define IO_INR_SCC0A_TXERR  30  /* SCC0A transmit memory read error */
0031 #define IO_INR_SCC0A_RXDMA  29  /* SCC0A receive half page */
0032 #define IO_INR_SCC0A_RXERR  28  /* SCC0A receive overrun */
0033 #define IO_INR_ASC_DMA      19  /* ASC buffer pointer loaded */
0034 #define IO_INR_ASC_ERR      18  /* ASC page overrun */
0035 #define IO_INR_ASC_MERR     17  /* ASC memory read error */
0036 #define IO_INR_LANCE_MERR   16  /* LANCE memory read error */
0037
0038                     /* except Maxine */
0039 #define IO_INR_SCC1A_TXDMA  27  /* SCC1A transmit page end */
0040 #define IO_INR_SCC1A_TXERR  26  /* SCC1A transmit memory read error */
0041 #define IO_INR_SCC1A_RXDMA  25  /* SCC1A receive half page */
0042 #define IO_INR_SCC1A_RXERR  24  /* SCC1A receive overrun */
0043 #define IO_INR_RES_23       23  /* unused */
0044 #define IO_INR_RES_22       22  /* unused */
0045 #define IO_INR_RES_21       21  /* unused */
0046 #define IO_INR_RES_20       20  /* unused */
0047
0048                     /* Maxine */
0049 #define IO_INR_AB_TXDMA     27  /* ACCESS.bus transmit page end */
0050 #define IO_INR_AB_TXERR     26  /* ACCESS.bus xmit memory read error */
0051 #define IO_INR_AB_RXDMA     25  /* ACCESS.bus receive half page */
0052 #define IO_INR_AB_RXERR     24  /* ACCESS.bus receive overrun */
0053 #define IO_INR_FLOPPY_ERR   23  /* FDC error */
0054 #define IO_INR_ISDN_TXDMA   22  /* ISDN xmit buffer pointer loaded */
0055 #define IO_INR_ISDN_RXDMA   21  /* ISDN recv buffer pointer loaded */
0056 #define IO_INR_ISDN_ERR     20  /* ISDN memory read/overrun error */
0057
0058 #define IO_INR_DMA      16  /* first DMA IRQ */
0059
0060 /*
0061  * The lower 16 bits are system-specific and thus defined in
0062  * system-specific headers.
0063  */
0064
0065
0066 #define IO_IRQ_BASE     8   /* first IRQ assigned to I/O ASIC */
0067 #define IO_IRQ_LINES        32  /* number of I/O ASIC interrupts */
0068
0069 #define IO_IRQ_NR(n)        ((n) + IO_IRQ_BASE)
0070 #define IO_IRQ_MASK(n)      (1 << (n))
0071 #define IO_IRQ_ALL      0x0000ffff
0072 #define IO_IRQ_DMA      0xffff0000
0073
0074 #endif /* __ASM_DEC_IOASIC_INTS_H */