asm/dec/ioasic_addrs.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Definitions for the address map in the JUNKIO Asic
0007  *
0008  * Created with Information from:
0009  *
0010  * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
0011  *
0012  * and the Mach Sources
0013  *
0014  * Copyright (C) 199x  the Anonymous
0015  * Copyright (C) 2002, 2003  Maciej W. Rozycki
0016  */
0017
0018 #ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
0019 #define __ASM_MIPS_DEC_IOASIC_ADDRS_H
0020
0021 #define IOASIC_SLOT_SIZE 0x00040000
0022
0023 /*
0024  * Address ranges decoded by the I/O ASIC for onboard devices.
0025  */
0026 #define IOASIC_SYS_ROM  (0*IOASIC_SLOT_SIZE)    /* system board ROM */
0027 #define IOASIC_IOCTL    (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
0028 #define IOASIC_ESAR (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
0029 #define IOASIC_LANCE    (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
0030 #define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
0031 #define IOASIC_VDAC_HI  (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
0032 #define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
0033 #define IOASIC_VDAC_LO  (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
0034 #define IOASIC_TOY  (8*IOASIC_SLOT_SIZE)    /* RTC */
0035 #define IOASIC_ISDN (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
0036 #define IOASIC_ERRADDR  (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
0037 #define IOASIC_CHKSYN   (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
0038 #define IOASIC_ACC_BUS  (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
0039 #define IOASIC_MCR  (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
0040 #define IOASIC_FLOPPY   (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
0041 #define IOASIC_SCSI (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
0042 #define IOASIC_FDC_DMA  (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
0043 #define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)   /* ??? */
0044 #define IOASIC_RES_15   (15*IOASIC_SLOT_SIZE)   /* unused? */
0045
0046
0047 /*
0048  * Offsets for I/O ASIC registers
0049  * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
0050  */
0051                     /* all systems */
0052 #define IO_REG_SCSI_DMA_P   0x00    /* SCSI DMA Pointer */
0053 #define IO_REG_SCSI_DMA_BP  0x10    /* SCSI DMA Buffer Pointer */
0054 #define IO_REG_LANCE_DMA_P  0x20    /* LANCE DMA Pointer */
0055 #define IO_REG_SCC0A_T_DMA_P    0x30    /* SCC0A Transmit DMA Pointer */
0056 #define IO_REG_SCC0A_R_DMA_P    0x40    /* SCC0A Receive DMA Pointer */
0057
0058                     /* except Maxine */
0059 #define IO_REG_SCC1A_T_DMA_P    0x50    /* SCC1A Transmit DMA Pointer */
0060 #define IO_REG_SCC1A_R_DMA_P    0x60    /* SCC1A Receive DMA Pointer */
0061
0062                     /* Maxine */
0063 #define IO_REG_AB_T_DMA_P   0x50    /* ACCESS.bus Transmit DMA Pointer */
0064 #define IO_REG_AB_R_DMA_P   0x60    /* ACCESS.bus Receive DMA Pointer */
0065 #define IO_REG_FLOPPY_DMA_P 0x70    /* Floppy DMA Pointer */
0066 #define IO_REG_ISDN_T_DMA_P 0x80    /* ISDN Transmit DMA Pointer */
0067 #define IO_REG_ISDN_T_DMA_BP    0x90    /* ISDN Transmit DMA Buffer Pointer */
0068 #define IO_REG_ISDN_R_DMA_P 0xa0    /* ISDN Receive DMA Pointer */
0069 #define IO_REG_ISDN_R_DMA_BP    0xb0    /* ISDN Receive DMA Buffer Pointer */
0070
0071                     /* all systems */
0072 #define IO_REG_DATA_0       0xc0    /* System Data Buffer 0 */
0073 #define IO_REG_DATA_1       0xd0    /* System Data Buffer 1 */
0074 #define IO_REG_DATA_2       0xe0    /* System Data Buffer 2 */
0075 #define IO_REG_DATA_3       0xf0    /* System Data Buffer 3 */
0076
0077                     /* all systems */
0078 #define IO_REG_SSR      0x100   /* System Support Register */
0079 #define IO_REG_SIR      0x110   /* System Interrupt Register */
0080 #define IO_REG_SIMR     0x120   /* System Interrupt Mask Reg. */
0081 #define IO_REG_SAR      0x130   /* System Address Register */
0082
0083                     /* Maxine */
0084 #define IO_REG_ISDN_T_DATA  0x140   /* ISDN Xmit Data Register */
0085 #define IO_REG_ISDN_R_DATA  0x150   /* ISDN Receive Data Register */
0086
0087                     /* all systems */
0088 #define IO_REG_LANCE_SLOT   0x160   /* LANCE I/O Slot Register */
0089 #define IO_REG_SCSI_SLOT    0x170   /* SCSI Slot Register */
0090 #define IO_REG_SCC0A_SLOT   0x180   /* SCC0A DMA Slot Register */
0091
0092                     /* except Maxine */
0093 #define IO_REG_SCC1A_SLOT   0x190   /* SCC1A DMA Slot Register */
0094
0095                     /* Maxine */
0096 #define IO_REG_AB_SLOT      0x190   /* ACCESS.bus DMA Slot Register */
0097 #define IO_REG_FLOPPY_SLOT  0x1a0   /* Floppy Slot Register */
0098
0099                     /* all systems */
0100 #define IO_REG_SCSI_SCR     0x1b0   /* SCSI Partial-Word DMA Control */
0101 #define IO_REG_SCSI_SDR0    0x1c0   /* SCSI DMA Partial Word 0 */
0102 #define IO_REG_SCSI_SDR1    0x1d0   /* SCSI DMA Partial Word 1 */
0103 #define IO_REG_FCTR     0x1e0   /* Free-Running Counter */
0104 #define IO_REG_RES_31       0x1f0   /* unused */
0105
0106
0107 /*
0108  * The upper 16 bits of the System Support Register are a part of the
0109  * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
0110  * machines.  The exception is the Maxine, which makes use of the
0111  * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
0112  * wiring.
0113  */
0114                         /* all systems */
0115 #define IO_SSR_SCC0A_TX_DMA_EN  (1<<31)     /* SCC0A transmit DMA enable */
0116 #define IO_SSR_SCC0A_RX_DMA_EN  (1<<30)     /* SCC0A receive DMA enable */
0117 #define IO_SSR_RES_27       (1<<27)     /* unused */
0118 #define IO_SSR_RES_26       (1<<26)     /* unused */
0119 #define IO_SSR_RES_25       (1<<25)     /* unused */
0120 #define IO_SSR_RES_24       (1<<24)     /* unused */
0121 #define IO_SSR_RES_23       (1<<23)     /* unused */
0122 #define IO_SSR_SCSI_DMA_DIR (1<<18)     /* SCSI DMA direction */
0123 #define IO_SSR_SCSI_DMA_EN  (1<<17)     /* SCSI DMA enable */
0124 #define IO_SSR_LANCE_DMA_EN (1<<16)     /* LANCE DMA enable */
0125
0126                         /* except Maxine */
0127 #define IO_SSR_SCC1A_TX_DMA_EN  (1<<29)     /* SCC1A transmit DMA enable */
0128 #define IO_SSR_SCC1A_RX_DMA_EN  (1<<28)     /* SCC1A receive DMA enable */
0129 #define IO_SSR_RES_22       (1<<22)     /* unused */
0130 #define IO_SSR_RES_21       (1<<21)     /* unused */
0131 #define IO_SSR_RES_20       (1<<20)     /* unused */
0132 #define IO_SSR_RES_19       (1<<19)     /* unused */
0133
0134                         /* Maxine */
0135 #define IO_SSR_AB_TX_DMA_EN (1<<29)     /* ACCESS.bus xmit DMA enable */
0136 #define IO_SSR_AB_RX_DMA_EN (1<<28)     /* ACCESS.bus recv DMA enable */
0137 #define IO_SSR_FLOPPY_DMA_DIR   (1<<22)     /* Floppy DMA direction */
0138 #define IO_SSR_FLOPPY_DMA_EN    (1<<21)     /* Floppy DMA enable */
0139 #define IO_SSR_ISDN_TX_DMA_EN   (1<<20)     /* ISDN transmit DMA enable */
0140 #define IO_SSR_ISDN_RX_DMA_EN   (1<<19)     /* ISDN receive DMA enable */
0141
0142 /*
0143  * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
0144  * defined here.  The rest is defined in system-specific headers.
0145  */
0146 #define KN0X_IO_SSR_DIAGDN  (1<<15)     /* diagnostic jumper */
0147 #define KN0X_IO_SSR_SCC_RST (1<<11)     /* ~SCC0,1 (Z85C30) reset */
0148 #define KN0X_IO_SSR_RTC_RST (1<<10)     /* ~RTC (DS1287) reset */
0149 #define KN0X_IO_SSR_ASC_RST (1<<9)      /* ~ASC (NCR53C94) reset */
0150 #define KN0X_IO_SSR_LANCE_RST   (1<<8)      /* ~LANCE (Am7990) reset */
0151
0152 #endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */