asm/dec/interrupts.h

0001 /*
0002  * Miscellaneous definitions used to initialise the interrupt vector table
0003  * with the machine-specific interrupt routines.
0004  *
0005  * This file is subject to the terms and conditions of the GNU General Public
0006  * License.  See the file "COPYING" in the main directory of this archive
0007  * for more details.
0008  *
0009  * Copyright (C) 1997 by Paul M. Antoine.
0010  * reworked 1998 by Harald Koerfgen.
0011  * Copyright (C) 2001, 2002, 2003  Maciej W. Rozycki
0012  */
0013
0014 #ifndef __ASM_DEC_INTERRUPTS_H
0015 #define __ASM_DEC_INTERRUPTS_H
0016
0017 #include <irq.h>
0018 #include <asm/mipsregs.h>
0019
0020
0021 /*
0022  * The list of possible system devices which provide an
0023  * interrupt.  Not all devices exist on a given system.
0024  */
0025 #define DEC_IRQ_CASCADE     0   /* cascade from CSR or I/O ASIC */
0026
0027 /* Ordinary interrupts */
0028 #define DEC_IRQ_AB_RECV     1   /* ACCESS.bus receive */
0029 #define DEC_IRQ_AB_XMIT     2   /* ACCESS.bus transmit */
0030 #define DEC_IRQ_DZ11        3   /* DZ11 (DC7085) serial */
0031 #define DEC_IRQ_ASC     4   /* ASC (NCR53C94) SCSI */
0032 #define DEC_IRQ_FLOPPY      5   /* 82077 FDC */
0033 #define DEC_IRQ_FPU     6   /* R3k FPU */
0034 #define DEC_IRQ_HALT        7   /* HALT button or from ACCESS.Bus */
0035 #define DEC_IRQ_ISDN        8   /* Am79C30A ISDN */
0036 #define DEC_IRQ_LANCE       9   /* LANCE (Am7990) Ethernet */
0037 #define DEC_IRQ_BUS     10  /* memory, I/O bus read/write errors */
0038 #define DEC_IRQ_PSU     11  /* power supply unit warning */
0039 #define DEC_IRQ_RTC     12  /* DS1287 RTC */
0040 #define DEC_IRQ_SCC0        13  /* SCC (Z85C30) serial #0 */
0041 #define DEC_IRQ_SCC1        14  /* SCC (Z85C30) serial #1 */
0042 #define DEC_IRQ_SII     15  /* SII (DC7061) SCSI */
0043 #define DEC_IRQ_TC0     16  /* TURBOchannel slot #0 */
0044 #define DEC_IRQ_TC1     17  /* TURBOchannel slot #1 */
0045 #define DEC_IRQ_TC2     18  /* TURBOchannel slot #2 */
0046 #define DEC_IRQ_TIMER       19  /* ARC periodic timer */
0047 #define DEC_IRQ_VIDEO       20  /* framebuffer */
0048
0049 /* I/O ASIC DMA interrupts */
0050 #define DEC_IRQ_ASC_MERR    21  /* ASC memory read error */
0051 #define DEC_IRQ_ASC_ERR     22  /* ASC page overrun */
0052 #define DEC_IRQ_ASC_DMA     23  /* ASC buffer pointer loaded */
0053 #define DEC_IRQ_FLOPPY_ERR  24  /* FDC error */
0054 #define DEC_IRQ_ISDN_ERR    25  /* ISDN memory read/overrun error */
0055 #define DEC_IRQ_ISDN_RXDMA  26  /* ISDN recv buffer pointer loaded */
0056 #define DEC_IRQ_ISDN_TXDMA  27  /* ISDN xmit buffer pointer loaded */
0057 #define DEC_IRQ_LANCE_MERR  28  /* LANCE memory read error */
0058 #define DEC_IRQ_SCC0A_RXERR 29  /* SCC0A (printer) receive overrun */
0059 #define DEC_IRQ_SCC0A_RXDMA 30  /* SCC0A receive half page */
0060 #define DEC_IRQ_SCC0A_TXERR 31  /* SCC0A xmit memory read/overrun */
0061 #define DEC_IRQ_SCC0A_TXDMA 32  /* SCC0A transmit page end */
0062 #define DEC_IRQ_AB_RXERR    33  /* ACCESS.bus receive overrun */
0063 #define DEC_IRQ_AB_RXDMA    34  /* ACCESS.bus receive half page */
0064 #define DEC_IRQ_AB_TXERR    35  /* ACCESS.bus xmit memory read/ovrn */
0065 #define DEC_IRQ_AB_TXDMA    36  /* ACCESS.bus transmit page end */
0066 #define DEC_IRQ_SCC1A_RXERR 37  /* SCC1A (modem) receive overrun */
0067 #define DEC_IRQ_SCC1A_RXDMA 38  /* SCC1A receive half page */
0068 #define DEC_IRQ_SCC1A_TXERR 39  /* SCC1A xmit memory read/overrun */
0069 #define DEC_IRQ_SCC1A_TXDMA 40  /* SCC1A transmit page end */
0070
0071 /* TC5 & TC6 are virtual slots for KN02's onboard devices */
0072 #define DEC_IRQ_TC5     DEC_IRQ_ASC /* virtual PMAZ-AA */
0073 #define DEC_IRQ_TC6     DEC_IRQ_LANCE   /* virtual PMAD-AA */
0074
0075 #define DEC_NR_INTS     41
0076
0077
0078 /* Largest of cpu mask_nr tables. */
0079 #define DEC_MAX_CPU_INTS    6
0080 /* Largest of asic mask_nr tables. */
0081 #define DEC_MAX_ASIC_INTS   9
0082
0083
0084 /*
0085  * CPU interrupt bits common to all systems.
0086  */
0087 #define DEC_CPU_INR_FPU     7   /* R3k FPU */
0088 #define DEC_CPU_INR_SW1     1   /* software #1 */
0089 #define DEC_CPU_INR_SW0     0   /* software #0 */
0090
0091 #define DEC_CPU_IRQ_BASE    MIPS_CPU_IRQ_BASE   /* first IRQ assigned to CPU */
0092
0093 #define DEC_CPU_IRQ_NR(n)   ((n) + DEC_CPU_IRQ_BASE)
0094 #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
0095 #define DEC_CPU_IRQ_ALL     (0xff << CAUSEB_IP)
0096
0097
0098 #ifndef __ASSEMBLY__
0099
0100 /*
0101  * Interrupt table structures to hide differences between systems.
0102  */
0103 typedef union { int i; void *p; } int_ptr;
0104 extern int dec_interrupt[DEC_NR_INTS];
0105 extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
0106 extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
0107 extern int cpu_fpu_mask;
0108
0109
0110 /*
0111  * Common interrupt routine prototypes for all DECStations
0112  */
0113 extern void kn02_io_int(void);
0114 extern void kn02xa_io_int(void);
0115 extern void kn03_io_int(void);
0116 extern void asic_dma_int(void);
0117 extern void asic_all_int(void);
0118 extern void kn02_all_int(void);
0119 extern void cpu_all_int(void);
0120
0121 extern void dec_intr_unimplemented(void);
0122 extern void asic_intr_unimplemented(void);
0123
0124 #endif /* __ASSEMBLY__ */
0125
0126 #endif