include/asm/cpu-features.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2003, 2004 Ralf Baechle
0007  * Copyright (C) 2004  Maciej W. Rozycki
0008  */
0009 #ifndef __ASM_CPU_FEATURES_H
0010 #define __ASM_CPU_FEATURES_H
0011
0012 #include <asm/cpu.h>
0013 #include <asm/cpu-info.h>
0014 #include <asm/isa-rev.h>
0015 #include <cpu-feature-overrides.h>
0016
0017 #define __ase(ase)          (cpu_data[0].ases & (ase))
0018 #define __isa(isa)          (cpu_data[0].isa_level & (isa))
0019 #define __opt(opt)          (cpu_data[0].options & (opt))
0020
0021 /*
0022  * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
0023  * boot (typically by cpu_probe()).
0024  *
0025  * Note that these should only be used in cases where a kernel built for an
0026  * older ISA *cannot* run on a CPU which supports the feature in question. For
0027  * example this may be used for features introduced with MIPSr6, since a kernel
0028  * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
0029  * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
0030  * MIPSr2 CPU.
0031  */
0032 #define __isa_ge_and_ase(isa, ase)  ((MIPS_ISA_REV >= (isa)) && __ase(ase))
0033 #define __isa_ge_and_opt(isa, opt)  ((MIPS_ISA_REV >= (isa)) && __opt(opt))
0034
0035 /*
0036  * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
0037  * boot (typically by cpu_probe()).
0038  *
0039  * These are for use with features that are optional up until a particular ISA
0040  * revision & then become required.
0041  */
0042 #define __isa_ge_or_ase(isa, ase)   ((MIPS_ISA_REV >= (isa)) || __ase(ase))
0043 #define __isa_ge_or_opt(isa, opt)   ((MIPS_ISA_REV >= (isa)) || __opt(opt))
0044
0045 /*
0046  * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
0047  * boot (typically by cpu_probe()).
0048  *
0049  * These are for use with features that are optional up until a particular ISA
0050  * revision & are then removed - ie. no longer present in any CPU implementing
0051  * the given ISA revision.
0052  */
0053 #define __isa_lt_and_ase(isa, ase)  ((MIPS_ISA_REV < (isa)) && __ase(ase))
0054 #define __isa_lt_and_opt(isa, opt)  ((MIPS_ISA_REV < (isa)) && __opt(opt))
0055
0056 /*
0057  * Similarly allow for ISA level checks that take into account knowledge of the
0058  * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
0059  */
0060 #define __isa_ge_and_flag(isa, flag)    ((MIPS_ISA_REV >= (isa)) && __isa(flag))
0061 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag))
0062 #define __isa_lt_and_flag(isa, flag)    ((MIPS_ISA_REV < (isa)) && __isa(flag))
0063 #define __isa_range(ge, lt) \
0064     ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
0065 #define __isa_range_or_flag(ge, lt, flag) \
0066     (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
0067 #define __isa_range_and_ase(ge, lt, ase) \
0068     (__isa_range(ge, lt) && __ase(ase))
0069
0070 /*
0071  * SMP assumption: Options of CPU 0 are a superset of all processors.
0072  * This is true for all known MIPS systems.
0073  */
0074 #ifndef cpu_has_tlb
0075 #define cpu_has_tlb     __opt(MIPS_CPU_TLB)
0076 #endif
0077 #ifndef cpu_has_ftlb
0078 #define cpu_has_ftlb        __opt(MIPS_CPU_FTLB)
0079 #endif
0080 #ifndef cpu_has_tlbinv
0081 #define cpu_has_tlbinv      __opt(MIPS_CPU_TLBINV)
0082 #endif
0083 #ifndef cpu_has_segments
0084 #define cpu_has_segments    __opt(MIPS_CPU_SEGMENTS)
0085 #endif
0086 #ifndef cpu_has_eva
0087 #define cpu_has_eva     __opt(MIPS_CPU_EVA)
0088 #endif
0089 #ifndef cpu_has_htw
0090 #define cpu_has_htw     __opt(MIPS_CPU_HTW)
0091 #endif
0092 #ifndef cpu_has_ldpte
0093 #define cpu_has_ldpte       __opt(MIPS_CPU_LDPTE)
0094 #endif
0095 #ifndef cpu_has_rixiex
0096 #define cpu_has_rixiex      __isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
0097 #endif
0098 #ifndef cpu_has_maar
0099 #define cpu_has_maar        __opt(MIPS_CPU_MAAR)
0100 #endif
0101 #ifndef cpu_has_rw_llb
0102 #define cpu_has_rw_llb      __isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
0103 #endif
0104
0105 /*
0106  * For the moment we don't consider R6000 and R8000 so we can assume that
0107  * anything that doesn't support R4000-style exceptions and interrupts is
0108  * R3000-like.  Users should still treat these two macro definitions as
0109  * opaque.
0110  */
0111 #ifndef cpu_has_3kex
0112 #define cpu_has_3kex        (!cpu_has_4kex)
0113 #endif
0114 #ifndef cpu_has_4kex
0115 #define cpu_has_4kex        __isa_ge_or_opt(1, MIPS_CPU_4KEX)
0116 #endif
0117 #ifndef cpu_has_3k_cache
0118 #define cpu_has_3k_cache    __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
0119 #endif
0120 #ifndef cpu_has_4k_cache
0121 #define cpu_has_4k_cache    __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
0122 #endif
0123 #ifndef cpu_has_octeon_cache
0124 #define cpu_has_octeon_cache    0
0125 #endif
0126 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
0127 #ifndef cpu_has_fpu
0128 # ifdef CONFIG_MIPS_FP_SUPPORT
0129 #  define cpu_has_fpu       (current_cpu_data.options & MIPS_CPU_FPU)
0130 #  define raw_cpu_has_fpu   (raw_current_cpu_data.options & MIPS_CPU_FPU)
0131 # else
0132 #  define cpu_has_fpu       0
0133 #  define raw_cpu_has_fpu   0
0134 # endif
0135 #else
0136 # if cpu_has_fpu
0137 #  error "Forcing `cpu_has_fpu' to non-zero is not supported"
0138 # endif
0139 # define raw_cpu_has_fpu    cpu_has_fpu
0140 #endif
0141 #ifndef cpu_has_32fpr
0142 #define cpu_has_32fpr       __isa_ge_or_opt(1, MIPS_CPU_32FPR)
0143 #endif
0144 #ifndef cpu_has_counter
0145 #define cpu_has_counter     __opt(MIPS_CPU_COUNTER)
0146 #endif
0147 #ifndef cpu_has_watch
0148 #define cpu_has_watch       __opt(MIPS_CPU_WATCH)
0149 #endif
0150 #ifndef cpu_has_divec
0151 #define cpu_has_divec       __isa_ge_or_opt(1, MIPS_CPU_DIVEC)
0152 #endif
0153 #ifndef cpu_has_vce
0154 #define cpu_has_vce     __opt(MIPS_CPU_VCE)
0155 #endif
0156 #ifndef cpu_has_cache_cdex_p
0157 #define cpu_has_cache_cdex_p    __opt(MIPS_CPU_CACHE_CDEX_P)
0158 #endif
0159 #ifndef cpu_has_cache_cdex_s
0160 #define cpu_has_cache_cdex_s    __opt(MIPS_CPU_CACHE_CDEX_S)
0161 #endif
0162 #ifndef cpu_has_prefetch
0163 #define cpu_has_prefetch    __isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
0164 #endif
0165 #ifndef cpu_has_mcheck
0166 #define cpu_has_mcheck      __isa_ge_or_opt(1, MIPS_CPU_MCHECK)
0167 #endif
0168 #ifndef cpu_has_ejtag
0169 #define cpu_has_ejtag       __opt(MIPS_CPU_EJTAG)
0170 #endif
0171 #ifndef cpu_has_llsc
0172 #define cpu_has_llsc        __isa_ge_or_opt(1, MIPS_CPU_LLSC)
0173 #endif
0174 #ifndef kernel_uses_llsc
0175 #define kernel_uses_llsc    cpu_has_llsc
0176 #endif
0177 #ifndef cpu_has_guestctl0ext
0178 #define cpu_has_guestctl0ext    __opt(MIPS_CPU_GUESTCTL0EXT)
0179 #endif
0180 #ifndef cpu_has_guestctl1
0181 #define cpu_has_guestctl1   __opt(MIPS_CPU_GUESTCTL1)
0182 #endif
0183 #ifndef cpu_has_guestctl2
0184 #define cpu_has_guestctl2   __opt(MIPS_CPU_GUESTCTL2)
0185 #endif
0186 #ifndef cpu_has_guestid
0187 #define cpu_has_guestid     __opt(MIPS_CPU_GUESTID)
0188 #endif
0189 #ifndef cpu_has_drg
0190 #define cpu_has_drg     __opt(MIPS_CPU_DRG)
0191 #endif
0192 #ifndef cpu_has_mips16
0193 #define cpu_has_mips16      __isa_lt_and_ase(6, MIPS_ASE_MIPS16)
0194 #endif
0195 #ifndef cpu_has_mips16e2
0196 #define cpu_has_mips16e2    __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
0197 #endif
0198 #ifndef cpu_has_mdmx
0199 #define cpu_has_mdmx        __isa_lt_and_ase(6, MIPS_ASE_MDMX)
0200 #endif
0201 #ifndef cpu_has_mips3d
0202 #define cpu_has_mips3d      __isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
0203 #endif
0204 #ifndef cpu_has_smartmips
0205 #define cpu_has_smartmips   __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
0206 #endif
0207
0208 #ifndef cpu_has_rixi
0209 #define cpu_has_rixi        __isa_ge_or_opt(6, MIPS_CPU_RIXI)
0210 #endif
0211
0212 #ifndef cpu_has_mmips
0213 # if defined(__mips_micromips)
0214 #  define cpu_has_mmips     1
0215 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
0216 #  define cpu_has_mmips     __opt(MIPS_CPU_MICROMIPS)
0217 # else
0218 #  define cpu_has_mmips     0
0219 # endif
0220 #endif
0221
0222 #ifndef cpu_has_lpa
0223 #define cpu_has_lpa     __opt(MIPS_CPU_LPA)
0224 #endif
0225 #ifndef cpu_has_mvh
0226 #define cpu_has_mvh     __opt(MIPS_CPU_MVH)
0227 #endif
0228 #ifndef cpu_has_xpa
0229 #define cpu_has_xpa     (cpu_has_lpa && cpu_has_mvh)
0230 #endif
0231 #ifndef cpu_has_vtag_icache
0232 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
0233 #endif
0234 #ifndef cpu_has_dc_aliases
0235 #define cpu_has_dc_aliases  (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
0236 #endif
0237 #ifndef cpu_has_ic_fills_f_dc
0238 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
0239 #endif
0240 #ifndef cpu_has_pindexed_dcache
0241 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
0242 #endif
0243
0244 /*
0245  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
0246  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
0247  * don't.  For maintaining I-cache coherency this means we need to flush the
0248  * D-cache all the way back to whever the I-cache does refills from, so the
0249  * I-cache has a chance to see the new data at all.  Then we have to flush the
0250  * I-cache also.
0251  * Note we may have been rescheduled and may no longer be running on the CPU
0252  * that did the store so we can't optimize this into only doing the flush on
0253  * the local CPU.
0254  */
0255 #ifndef cpu_icache_snoops_remote_store
0256 #ifdef CONFIG_SMP
0257 #define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
0258 #else
0259 #define cpu_icache_snoops_remote_store  1
0260 #endif
0261 #endif
0262
0263 #ifndef cpu_has_mips_1
0264 # define cpu_has_mips_1     (MIPS_ISA_REV < 6)
0265 #endif
0266 #ifndef cpu_has_mips_2
0267 # define cpu_has_mips_2     __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
0268 #endif
0269 #ifndef cpu_has_mips_3
0270 # define cpu_has_mips_3     __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
0271 #endif
0272 #ifndef cpu_has_mips_4
0273 # define cpu_has_mips_4     __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
0274 #endif
0275 #ifndef cpu_has_mips_5
0276 # define cpu_has_mips_5     __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
0277 #endif
0278 #ifndef cpu_has_mips32r1
0279 # define cpu_has_mips32r1   __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
0280 #endif
0281 #ifndef cpu_has_mips32r2
0282 # define cpu_has_mips32r2   __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
0283 #endif
0284 #ifndef cpu_has_mips32r5
0285 # define cpu_has_mips32r5   __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
0286 #endif
0287 #ifndef cpu_has_mips32r6
0288 # define cpu_has_mips32r6   __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
0289 #endif
0290 #ifndef cpu_has_mips64r1
0291 # define cpu_has_mips64r1   (cpu_has_64bits && \
0292                  __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
0293 #endif
0294 #ifndef cpu_has_mips64r2
0295 # define cpu_has_mips64r2   (cpu_has_64bits && \
0296                  __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
0297 #endif
0298 #ifndef cpu_has_mips64r5
0299 # define cpu_has_mips64r5   (cpu_has_64bits && \
0300                  __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
0301 #endif
0302 #ifndef cpu_has_mips64r6
0303 # define cpu_has_mips64r6   __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
0304 #endif
0305
0306 /*
0307  * Shortcuts ...
0308  */
0309 #define cpu_has_mips_2_3_4_5    (cpu_has_mips_2 | cpu_has_mips_3_4_5)
0310 #define cpu_has_mips_3_4_5  (cpu_has_mips_3 | cpu_has_mips_4_5)
0311 #define cpu_has_mips_4_5    (cpu_has_mips_4 | cpu_has_mips_5)
0312
0313 #define cpu_has_mips_2_3_4_5_r  (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
0314 #define cpu_has_mips_3_4_5_r    (cpu_has_mips_3 | cpu_has_mips_4_5_r)
0315 #define cpu_has_mips_4_5_r  (cpu_has_mips_4 | cpu_has_mips_5_r)
0316 #define cpu_has_mips_5_r    (cpu_has_mips_5 | cpu_has_mips_r)
0317
0318 #define cpu_has_mips_3_4_5_64_r2_r6                 \
0319                 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
0320 #define cpu_has_mips_4_5_64_r2_r6                   \
0321                 (cpu_has_mips_4_5 | cpu_has_mips64r1 |  \
0322                  cpu_has_mips_r2 | cpu_has_mips_r5 | \
0323                  cpu_has_mips_r6)
0324
0325 #define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
0326              cpu_has_mips32r5 | cpu_has_mips32r6)
0327 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | \
0328              cpu_has_mips64r5 | cpu_has_mips64r6)
0329 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
0330 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
0331 #define cpu_has_mips_r5 (cpu_has_mips32r5 | cpu_has_mips64r5)
0332 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6)
0333 #define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
0334              cpu_has_mips32r5 | cpu_has_mips32r6 | \
0335              cpu_has_mips64r1 | cpu_has_mips64r2 | \
0336              cpu_has_mips64r5 | cpu_has_mips64r6)
0337
0338 /* MIPSR2 - MIPSR6 have a lot of similarities */
0339 #define cpu_has_mips_r2_r6  (cpu_has_mips_r2 | cpu_has_mips_r5 | \
0340                  cpu_has_mips_r6)
0341
0342 /*
0343  * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
0344  *
0345  * Returns non-zero value if the current processor implementation requires
0346  * an IHB instruction to deal with an instruction hazard as per MIPS R2
0347  * architecture specification, zero otherwise.
0348  */
0349 #ifndef cpu_has_mips_r2_exec_hazard
0350 #define cpu_has_mips_r2_exec_hazard                 \
0351 ({                                  \
0352     int __res;                          \
0353                                     \
0354     switch (current_cpu_type()) {                   \
0355     case CPU_M14KC:                         \
0356     case CPU_74K:                           \
0357     case CPU_1074K:                         \
0358     case CPU_PROAPTIV:                      \
0359     case CPU_P5600:                         \
0360     case CPU_M5150:                         \
0361     case CPU_QEMU_GENERIC:                      \
0362     case CPU_CAVIUM_OCTEON:                     \
0363     case CPU_CAVIUM_OCTEON_PLUS:                    \
0364     case CPU_CAVIUM_OCTEON2:                    \
0365     case CPU_CAVIUM_OCTEON3:                    \
0366         __res = 0;                      \
0367         break;                          \
0368                                     \
0369     default:                            \
0370         __res = 1;                      \
0371     }                               \
0372                                     \
0373     __res;                              \
0374 })
0375 #endif
0376
0377 /*
0378  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
0379  * pre-MIPS32/MIPS64 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
0380  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
0381  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
0382  */
0383 #ifndef cpu_has_clo_clz
0384 #define cpu_has_clo_clz cpu_has_mips_r
0385 #endif
0386
0387 /*
0388  * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
0389  * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
0390  * This indicates the availability of WSBH and in case of 64 bit CPUs also
0391  * DSBH and DSHD.
0392  */
0393 #ifndef cpu_has_wsbh
0394 #define cpu_has_wsbh        cpu_has_mips_r2
0395 #endif
0396
0397 #ifndef cpu_has_dsp
0398 #define cpu_has_dsp     __ase(MIPS_ASE_DSP)
0399 #endif
0400
0401 #ifndef cpu_has_dsp2
0402 #define cpu_has_dsp2        __ase(MIPS_ASE_DSP2P)
0403 #endif
0404
0405 #ifndef cpu_has_dsp3
0406 #define cpu_has_dsp3        __ase(MIPS_ASE_DSP3)
0407 #endif
0408
0409 #ifndef cpu_has_loongson_mmi
0410 #define cpu_has_loongson_mmi        __ase(MIPS_ASE_LOONGSON_MMI)
0411 #endif
0412
0413 #ifndef cpu_has_loongson_cam
0414 #define cpu_has_loongson_cam        __ase(MIPS_ASE_LOONGSON_CAM)
0415 #endif
0416
0417 #ifndef cpu_has_loongson_ext
0418 #define cpu_has_loongson_ext        __ase(MIPS_ASE_LOONGSON_EXT)
0419 #endif
0420
0421 #ifndef cpu_has_loongson_ext2
0422 #define cpu_has_loongson_ext2       __ase(MIPS_ASE_LOONGSON_EXT2)
0423 #endif
0424
0425 #ifndef cpu_has_mipsmt
0426 #define cpu_has_mipsmt      __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
0427 #endif
0428
0429 #ifndef cpu_has_vp
0430 #define cpu_has_vp      __isa_ge_and_opt(6, MIPS_CPU_VP)
0431 #endif
0432
0433 #ifndef cpu_has_userlocal
0434 #define cpu_has_userlocal   __isa_ge_or_opt(6, MIPS_CPU_ULRI)
0435 #endif
0436
0437 #ifdef CONFIG_32BIT
0438 # ifndef cpu_has_nofpuex
0439 # define cpu_has_nofpuex    __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
0440 # endif
0441 # ifndef cpu_has_64bits
0442 # define cpu_has_64bits     (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
0443 # endif
0444 # ifndef cpu_has_64bit_zero_reg
0445 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
0446 # endif
0447 # ifndef cpu_has_64bit_gp_regs
0448 # define cpu_has_64bit_gp_regs      0
0449 # endif
0450 # ifndef cpu_vmbits
0451 # define cpu_vmbits 31
0452 # endif
0453 #endif
0454
0455 #ifdef CONFIG_64BIT
0456 # ifndef cpu_has_nofpuex
0457 # define cpu_has_nofpuex        0
0458 # endif
0459 # ifndef cpu_has_64bits
0460 # define cpu_has_64bits         1
0461 # endif
0462 # ifndef cpu_has_64bit_zero_reg
0463 # define cpu_has_64bit_zero_reg     1
0464 # endif
0465 # ifndef cpu_has_64bit_gp_regs
0466 # define cpu_has_64bit_gp_regs      1
0467 # endif
0468 # ifndef cpu_vmbits
0469 # define cpu_vmbits cpu_data[0].vmbits
0470 # define __NEED_VMBITS_PROBE
0471 # endif
0472 #endif
0473
0474 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
0475 # define cpu_has_vint       __opt(MIPS_CPU_VINT)
0476 #elif !defined(cpu_has_vint)
0477 # define cpu_has_vint           0
0478 #endif
0479
0480 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
0481 # define cpu_has_veic       __opt(MIPS_CPU_VEIC)
0482 #elif !defined(cpu_has_veic)
0483 # define cpu_has_veic           0
0484 #endif
0485
0486 #ifndef cpu_has_inclusive_pcaches
0487 #define cpu_has_inclusive_pcaches   __opt(MIPS_CPU_INCLUSIVE_CACHES)
0488 #endif
0489
0490 #ifndef cpu_dcache_line_size
0491 #define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
0492 #endif
0493 #ifndef cpu_icache_line_size
0494 #define cpu_icache_line_size()  cpu_data[0].icache.linesz
0495 #endif
0496 #ifndef cpu_scache_line_size
0497 #define cpu_scache_line_size()  cpu_data[0].scache.linesz
0498 #endif
0499 #ifndef cpu_tcache_line_size
0500 #define cpu_tcache_line_size()  cpu_data[0].tcache.linesz
0501 #endif
0502
0503 #ifndef cpu_hwrena_impl_bits
0504 #define cpu_hwrena_impl_bits        0
0505 #endif
0506
0507 #ifndef cpu_has_perf_cntr_intr_bit
0508 #define cpu_has_perf_cntr_intr_bit  __opt(MIPS_CPU_PCI)
0509 #endif
0510
0511 #ifndef cpu_has_vz
0512 #define cpu_has_vz      __ase(MIPS_ASE_VZ)
0513 #endif
0514
0515 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
0516 # define cpu_has_msa        __ase(MIPS_ASE_MSA)
0517 #elif !defined(cpu_has_msa)
0518 # define cpu_has_msa        0
0519 #endif
0520
0521 #ifndef cpu_has_ufr
0522 # define cpu_has_ufr        __opt(MIPS_CPU_UFR)
0523 #endif
0524
0525 #ifndef cpu_has_fre
0526 # define cpu_has_fre        __opt(MIPS_CPU_FRE)
0527 #endif
0528
0529 #ifndef cpu_has_cdmm
0530 # define cpu_has_cdmm       __opt(MIPS_CPU_CDMM)
0531 #endif
0532
0533 #ifndef cpu_has_small_pages
0534 # define cpu_has_small_pages    __opt(MIPS_CPU_SP)
0535 #endif
0536
0537 #ifndef cpu_has_nan_legacy
0538 #define cpu_has_nan_legacy  __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
0539 #endif
0540 #ifndef cpu_has_nan_2008
0541 #define cpu_has_nan_2008    __isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
0542 #endif
0543
0544 #ifndef cpu_has_ebase_wg
0545 # define cpu_has_ebase_wg   __opt(MIPS_CPU_EBASE_WG)
0546 #endif
0547
0548 #ifndef cpu_has_badinstr
0549 # define cpu_has_badinstr   __isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
0550 #endif
0551
0552 #ifndef cpu_has_badinstrp
0553 # define cpu_has_badinstrp  __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
0554 #endif
0555
0556 #ifndef cpu_has_contextconfig
0557 # define cpu_has_contextconfig  __opt(MIPS_CPU_CTXTC)
0558 #endif
0559
0560 #ifndef cpu_has_perf
0561 # define cpu_has_perf       __opt(MIPS_CPU_PERF)
0562 #endif
0563
0564 #ifndef cpu_has_mac2008_only
0565 # define cpu_has_mac2008_only   __opt(MIPS_CPU_MAC_2008_ONLY)
0566 #endif
0567
0568 #ifndef cpu_has_ftlbparex
0569 # define cpu_has_ftlbparex  __opt(MIPS_CPU_FTLBPAREX)
0570 #endif
0571
0572 #ifndef cpu_has_gsexcex
0573 # define cpu_has_gsexcex    __opt(MIPS_CPU_GSEXCEX)
0574 #endif
0575
0576 #ifdef CONFIG_SMP
0577 /*
0578  * Some systems share FTLB RAMs between threads within a core (siblings in
0579  * kernel parlance). This means that FTLB entries may become invalid at almost
0580  * any point when an entry is evicted due to a sibling thread writing an entry
0581  * to the shared FTLB RAM.
0582  *
0583  * This is only relevant to SMP systems, and the only systems that exhibit this
0584  * property implement MIPSr6 or higher so we constrain support for this to
0585  * kernels that will run on such systems.
0586  */
0587 # ifndef cpu_has_shared_ftlb_ram
0588 #  define cpu_has_shared_ftlb_ram \
0589     __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
0590 # endif
0591
0592 /*
0593  * Some systems take this a step further & share FTLB entries between siblings.
0594  * This is implemented as TLB writes happening as usual, but if an entry
0595  * written by a sibling exists in the shared FTLB for a translation which would
0596  * otherwise cause a TLB refill exception then the CPU will use the entry
0597  * written by its sibling rather than triggering a refill & writing a matching
0598  * TLB entry for itself.
0599  *
0600  * This is naturally only valid if a TLB entry is known to be suitable for use
0601  * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
0602  * rather than ASIDs or when a TLB entry is marked global.
0603  */
0604 # ifndef cpu_has_shared_ftlb_entries
0605 #  define cpu_has_shared_ftlb_entries \
0606     __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
0607 # endif
0608 #endif /* SMP */
0609
0610 #ifndef cpu_has_shared_ftlb_ram
0611 # define cpu_has_shared_ftlb_ram 0
0612 #endif
0613 #ifndef cpu_has_shared_ftlb_entries
0614 # define cpu_has_shared_ftlb_entries 0
0615 #endif
0616
0617 #ifdef CONFIG_MIPS_MT_SMP
0618 # define cpu_has_mipsmt_pertccounters \
0619     __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
0620 #else
0621 # define cpu_has_mipsmt_pertccounters 0
0622 #endif /* CONFIG_MIPS_MT_SMP */
0623
0624 /*
0625  * We only enable MMID support for configurations which natively support 64 bit
0626  * atomics because getting good performance from the allocator relies upon
0627  * efficient atomic64_*() functions.
0628  */
0629 #ifndef cpu_has_mmid
0630 # ifdef CONFIG_GENERIC_ATOMIC64
0631 #  define cpu_has_mmid      0
0632 # else
0633 #  define cpu_has_mmid      __isa_ge_and_opt(6, MIPS_CPU_MMID)
0634 # endif
0635 #endif
0636
0637 #ifndef cpu_has_mm_sysad
0638 # define cpu_has_mm_sysad   __opt(MIPS_CPU_MM_SYSAD)
0639 #endif
0640
0641 #ifndef cpu_has_mm_full
0642 # define cpu_has_mm_full    __opt(MIPS_CPU_MM_FULL)
0643 #endif
0644
0645 /*
0646  * Guest capabilities
0647  */
0648 #ifndef cpu_guest_has_conf1
0649 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1))
0650 #endif
0651 #ifndef cpu_guest_has_conf2
0652 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2))
0653 #endif
0654 #ifndef cpu_guest_has_conf3
0655 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3))
0656 #endif
0657 #ifndef cpu_guest_has_conf4
0658 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4))
0659 #endif
0660 #ifndef cpu_guest_has_conf5
0661 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5))
0662 #endif
0663 #ifndef cpu_guest_has_conf6
0664 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6))
0665 #endif
0666 #ifndef cpu_guest_has_conf7
0667 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7))
0668 #endif
0669 #ifndef cpu_guest_has_fpu
0670 #define cpu_guest_has_fpu   (cpu_data[0].guest.options & MIPS_CPU_FPU)
0671 #endif
0672 #ifndef cpu_guest_has_watch
0673 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH)
0674 #endif
0675 #ifndef cpu_guest_has_contextconfig
0676 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
0677 #endif
0678 #ifndef cpu_guest_has_segments
0679 #define cpu_guest_has_segments  (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
0680 #endif
0681 #ifndef cpu_guest_has_badinstr
0682 #define cpu_guest_has_badinstr  (cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
0683 #endif
0684 #ifndef cpu_guest_has_badinstrp
0685 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
0686 #endif
0687 #ifndef cpu_guest_has_htw
0688 #define cpu_guest_has_htw   (cpu_data[0].guest.options & MIPS_CPU_HTW)
0689 #endif
0690 #ifndef cpu_guest_has_ldpte
0691 #define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE)
0692 #endif
0693 #ifndef cpu_guest_has_mvh
0694 #define cpu_guest_has_mvh   (cpu_data[0].guest.options & MIPS_CPU_MVH)
0695 #endif
0696 #ifndef cpu_guest_has_msa
0697 #define cpu_guest_has_msa   (cpu_data[0].guest.ases & MIPS_ASE_MSA)
0698 #endif
0699 #ifndef cpu_guest_has_kscr
0700 #define cpu_guest_has_kscr(n)   (cpu_data[0].guest.kscratch_mask & (1u << (n)))
0701 #endif
0702 #ifndef cpu_guest_has_rw_llb
0703 #define cpu_guest_has_rw_llb    (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
0704 #endif
0705 #ifndef cpu_guest_has_perf
0706 #define cpu_guest_has_perf  (cpu_data[0].guest.options & MIPS_CPU_PERF)
0707 #endif
0708 #ifndef cpu_guest_has_maar
0709 #define cpu_guest_has_maar  (cpu_data[0].guest.options & MIPS_CPU_MAAR)
0710 #endif
0711 #ifndef cpu_guest_has_userlocal
0712 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI)
0713 #endif
0714
0715 /*
0716  * Guest dynamic capabilities
0717  */
0718 #ifndef cpu_guest_has_dyn_fpu
0719 #define cpu_guest_has_dyn_fpu   (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
0720 #endif
0721 #ifndef cpu_guest_has_dyn_watch
0722 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
0723 #endif
0724 #ifndef cpu_guest_has_dyn_contextconfig
0725 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
0726 #endif
0727 #ifndef cpu_guest_has_dyn_perf
0728 #define cpu_guest_has_dyn_perf  (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
0729 #endif
0730 #ifndef cpu_guest_has_dyn_msa
0731 #define cpu_guest_has_dyn_msa   (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
0732 #endif
0733 #ifndef cpu_guest_has_dyn_maar
0734 #define cpu_guest_has_dyn_maar  (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
0735 #endif
0736
0737 #endif /* __ASM_CPU_FEATURES_H */