include/asm/cacheops.h

0001 /*
0002  * Cache operations for the cache instruction.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
0009  * (C) Copyright 1999 Silicon Graphics, Inc.
0010  */
0011 #ifndef __ASM_CACHEOPS_H
0012 #define __ASM_CACHEOPS_H
0013
0014 /*
0015  * Most cache ops are split into a 2 bit field identifying the cache, and a 3
0016  * bit field identifying the cache operation.
0017  */
0018 #define CacheOp_Cache           0x03
0019 #define CacheOp_Op          0x1c
0020
0021 #define Cache_I             0x00
0022 #define Cache_D             0x01
0023 #define Cache_T             0x02
0024 #define Cache_V             0x02 /* Loongson-3 */
0025 #define Cache_S             0x03
0026
0027 #define Index_Writeback_Inv     0x00
0028 #define Index_Load_Tag          0x04
0029 #define Index_Store_Tag         0x08
0030 #define Hit_Invalidate          0x10
0031 #define Hit_Writeback_Inv       0x14    /* not with Cache_I though */
0032 #define Hit_Writeback           0x18
0033
0034 /*
0035  * Cache Operations available on all MIPS processors with R4000-style caches
0036  */
0037 #define Index_Invalidate_I      (Cache_I | Index_Writeback_Inv)
0038 #define Index_Writeback_Inv_D       (Cache_D | Index_Writeback_Inv)
0039 #define Index_Load_Tag_I        (Cache_I | Index_Load_Tag)
0040 #define Index_Load_Tag_D        (Cache_D | Index_Load_Tag)
0041 #define Index_Store_Tag_I       (Cache_I | Index_Store_Tag)
0042 #define Index_Store_Tag_D       (Cache_D | Index_Store_Tag)
0043 #define Hit_Invalidate_I        (Cache_I | Hit_Invalidate)
0044 #define Hit_Invalidate_D        (Cache_D | Hit_Invalidate)
0045 #define Hit_Writeback_Inv_D     (Cache_D | Hit_Writeback_Inv)
0046
0047 /*
0048  * R4000-specific cacheops
0049  */
0050 #define Create_Dirty_Excl_D     (Cache_D | 0x0c)
0051 #define Fill_I              (Cache_I | 0x14)
0052 #define Hit_Writeback_I         (Cache_I | Hit_Writeback)
0053 #define Hit_Writeback_D         (Cache_D | Hit_Writeback)
0054
0055 /*
0056  * R4000SC and R4400SC-specific cacheops
0057  */
0058 #define Cache_SI            0x02
0059 #define Cache_SD            0x03
0060
0061 #define Index_Invalidate_SI     (Cache_SI | Index_Writeback_Inv)
0062 #define Index_Writeback_Inv_SD      (Cache_SD | Index_Writeback_Inv)
0063 #define Index_Load_Tag_SI       (Cache_SI | Index_Load_Tag)
0064 #define Index_Load_Tag_SD       (Cache_SD | Index_Load_Tag)
0065 #define Index_Store_Tag_SI      (Cache_SI | Index_Store_Tag)
0066 #define Index_Store_Tag_SD      (Cache_SD | Index_Store_Tag)
0067 #define Create_Dirty_Excl_SD        (Cache_SD | 0x0c)
0068 #define Hit_Invalidate_SI       (Cache_SI | Hit_Invalidate)
0069 #define Hit_Invalidate_SD       (Cache_SD | Hit_Invalidate)
0070 #define Hit_Writeback_Inv_SD        (Cache_SD | Hit_Writeback_Inv)
0071 #define Hit_Writeback_SD        (Cache_SD | Hit_Writeback)
0072 #define Hit_Set_Virtual_SI      (Cache_SI | 0x1c)
0073 #define Hit_Set_Virtual_SD      (Cache_SD | 0x1c)
0074
0075 /*
0076  * R5000-specific cacheops
0077  */
0078 #define R5K_Page_Invalidate_S       (Cache_S | 0x14)
0079
0080 /*
0081  * RM7000-specific cacheops
0082  */
0083 #define Page_Invalidate_T       (Cache_T | 0x14)
0084 #define Index_Store_Tag_T       (Cache_T | Index_Store_Tag)
0085 #define Index_Load_Tag_T        (Cache_T | Index_Load_Tag)
0086
0087 /*
0088  * R10000-specific cacheops
0089  *
0090  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
0091  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
0092  */
0093 #define Index_Writeback_Inv_S       (Cache_S | Index_Writeback_Inv)
0094 #define Index_Load_Tag_S        (Cache_S | Index_Load_Tag)
0095 #define Index_Store_Tag_S       (Cache_S | Index_Store_Tag)
0096 #define Hit_Invalidate_S        (Cache_S | Hit_Invalidate)
0097 #define Cache_Barrier           0x14
0098 #define Hit_Writeback_Inv_S     (Cache_S | Hit_Writeback_Inv)
0099 #define Index_Load_Data_I       (Cache_I | 0x18)
0100 #define Index_Load_Data_D       (Cache_D | 0x18)
0101 #define Index_Load_Data_S       (Cache_S | 0x18)
0102 #define Index_Store_Data_I      (Cache_I | 0x1c)
0103 #define Index_Store_Data_D      (Cache_D | 0x1c)
0104 #define Index_Store_Data_S      (Cache_S | 0x1c)
0105
0106 /*
0107  * Loongson2-specific cacheops
0108  */
0109 #define Hit_Invalidate_I_Loongson2  (Cache_I | 0x00)
0110
0111 /*
0112  * Loongson3-specific cacheops
0113  */
0114 #define Index_Writeback_Inv_V       (Cache_V | Index_Writeback_Inv)
0115
0116 #endif  /* __ASM_CACHEOPS_H */