include/asm/bmips.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
0007  *
0008  * Definitions for BMIPS processors
0009  */
0010 #ifndef _ASM_BMIPS_H
0011 #define _ASM_BMIPS_H
0012
0013 #include <linux/compiler.h>
0014 #include <linux/linkage.h>
0015 #include <asm/addrspace.h>
0016 #include <asm/mipsregs.h>
0017 #include <asm/hazards.h>
0018
0019 /* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
0020 #define BMIPS_GET_CBR()         ((void __iomem *)(CKSEG1 | \
0021                      (unsigned long) \
0022                      ((read_c0_brcm_cbr() >> 18) << 18)))
0023
0024 #define BMIPS_RAC_CONFIG        0x00000000
0025 #define BMIPS_RAC_ADDRESS_RANGE     0x00000004
0026 #define BMIPS_RAC_CONFIG_1      0x00000008
0027 #define BMIPS_L2_CONFIG         0x0000000c
0028 #define BMIPS_LMB_CONTROL       0x0000001c
0029 #define BMIPS_SYSTEM_BASE       0x00000020
0030 #define BMIPS_PERF_GLOBAL_CONTROL   0x00020000
0031 #define BMIPS_PERF_CONTROL_0        0x00020004
0032 #define BMIPS_PERF_CONTROL_1        0x00020008
0033 #define BMIPS_PERF_COUNTER_0        0x00020010
0034 #define BMIPS_PERF_COUNTER_1        0x00020014
0035 #define BMIPS_PERF_COUNTER_2        0x00020018
0036 #define BMIPS_PERF_COUNTER_3        0x0002001c
0037 #define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
0038 #define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
0039
0040 #define BMIPS_NMI_RESET_VEC     0x80000000
0041 #define BMIPS_WARM_RESTART_VEC      0x80000380
0042
0043 #define ZSCM_REG_BASE           0x97000000
0044
0045 #if !defined(__ASSEMBLY__)
0046
0047 #include <linux/cpumask.h>
0048 #include <asm/r4kcache.h>
0049 #include <asm/smp-ops.h>
0050
0051 extern const struct plat_smp_ops bmips43xx_smp_ops;
0052 extern const struct plat_smp_ops bmips5000_smp_ops;
0053
0054 static inline int register_bmips_smp_ops(void)
0055 {
0056 #if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
0057     switch (current_cpu_type()) {
0058     case CPU_BMIPS32:
0059     case CPU_BMIPS3300:
0060         return register_up_smp_ops();
0061     case CPU_BMIPS4350:
0062     case CPU_BMIPS4380:
0063         register_smp_ops(&bmips43xx_smp_ops);
0064         break;
0065     case CPU_BMIPS5000:
0066         register_smp_ops(&bmips5000_smp_ops);
0067         break;
0068     default:
0069         return -ENODEV;
0070     }
0071
0072     return 0;
0073 #else
0074     return -ENODEV;
0075 #endif
0076 }
0077
0078 extern char bmips_reset_nmi_vec[];
0079 extern char bmips_reset_nmi_vec_end[];
0080 extern char bmips_smp_movevec[];
0081 extern char bmips_smp_int_vec[];
0082 extern char bmips_smp_int_vec_end[];
0083
0084 extern int bmips_smp_enabled;
0085 extern int bmips_cpu_offset;
0086 extern cpumask_t bmips_booted_mask;
0087 extern unsigned long bmips_tp1_irqs;
0088
0089 extern void bmips_ebase_setup(void);
0090 extern asmlinkage void plat_wired_tlb_setup(void);
0091 extern void bmips_cpu_setup(void);
0092
0093 static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
0094 {
0095     unsigned long ret;
0096
0097     barrier();
0098     cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
0099     __sync();
0100     _ssnop();
0101     _ssnop();
0102     _ssnop();
0103     _ssnop();
0104     _ssnop();
0105     _ssnop();
0106     _ssnop();
0107     ret = read_c0_ddatalo();
0108     _ssnop();
0109
0110     return ret;
0111 }
0112
0113 static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
0114 {
0115     write_c0_ddatalo(data);
0116     _ssnop();
0117     _ssnop();
0118     _ssnop();
0119     cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
0120     _ssnop();
0121     _ssnop();
0122     _ssnop();
0123     barrier();
0124 }
0125
0126 #endif /* !defined(__ASSEMBLY__) */
0127
0128 #endif /* _ASM_BMIPS_H */