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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2003 Ralf Baechle
0007  */
0008 #ifndef _ASM_ASMMACRO_H
0009 #define _ASM_ASMMACRO_H
0010 
0011 #include <asm/hazards.h>
0012 #include <asm/asm-offsets.h>
0013 #include <asm/msa.h>
0014 
0015 #ifdef CONFIG_32BIT
0016 #include <asm/asmmacro-32.h>
0017 #endif
0018 #ifdef CONFIG_64BIT
0019 #include <asm/asmmacro-64.h>
0020 #endif
0021 
0022 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
0023 #undef fp
0024 
0025 /*
0026  * Helper macros for generating raw instruction encodings.
0027  */
0028 #ifdef CONFIG_CPU_MICROMIPS
0029     .macro  insn32_if_mm enc
0030     .insn
0031     .hword ((\enc) >> 16)
0032     .hword ((\enc) & 0xffff)
0033     .endm
0034 
0035     .macro  insn_if_mips enc
0036     .endm
0037 #else
0038     .macro  insn32_if_mm enc
0039     .endm
0040 
0041     .macro  insn_if_mips enc
0042     .insn
0043     .word (\enc)
0044     .endm
0045 #endif
0046 
0047 #ifdef CONFIG_CPU_HAS_DIEI
0048     .macro  local_irq_enable reg=t0
0049     ei
0050     irq_enable_hazard
0051     .endm
0052 
0053     .macro  local_irq_disable reg=t0
0054     di
0055     irq_disable_hazard
0056     .endm
0057 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
0058     .macro  local_irq_enable reg=t0
0059     mfc0    \reg, CP0_STATUS
0060     ori \reg, \reg, 1
0061     mtc0    \reg, CP0_STATUS
0062     irq_enable_hazard
0063     .endm
0064 
0065     .macro  local_irq_disable reg=t0
0066 #ifdef CONFIG_PREEMPTION
0067     lw      \reg, TI_PRE_COUNT($28)
0068     addi    \reg, \reg, 1
0069     sw      \reg, TI_PRE_COUNT($28)
0070 #endif
0071     mfc0    \reg, CP0_STATUS
0072     ori \reg, \reg, 1
0073     xori    \reg, \reg, 1
0074     mtc0    \reg, CP0_STATUS
0075     irq_disable_hazard
0076 #ifdef CONFIG_PREEMPTION
0077     lw      \reg, TI_PRE_COUNT($28)
0078     addi    \reg, \reg, -1
0079     sw      \reg, TI_PRE_COUNT($28)
0080 #endif
0081     .endm
0082 #endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
0083 
0084     .macro  fpu_save_16even thread tmp=t0
0085     .set    push
0086     SET_HARDFLOAT
0087     cfc1    \tmp, fcr31
0088     sdc1    $f0,  THREAD_FPR0(\thread)
0089     sdc1    $f2,  THREAD_FPR2(\thread)
0090     sdc1    $f4,  THREAD_FPR4(\thread)
0091     sdc1    $f6,  THREAD_FPR6(\thread)
0092     sdc1    $f8,  THREAD_FPR8(\thread)
0093     sdc1    $f10, THREAD_FPR10(\thread)
0094     sdc1    $f12, THREAD_FPR12(\thread)
0095     sdc1    $f14, THREAD_FPR14(\thread)
0096     sdc1    $f16, THREAD_FPR16(\thread)
0097     sdc1    $f18, THREAD_FPR18(\thread)
0098     sdc1    $f20, THREAD_FPR20(\thread)
0099     sdc1    $f22, THREAD_FPR22(\thread)
0100     sdc1    $f24, THREAD_FPR24(\thread)
0101     sdc1    $f26, THREAD_FPR26(\thread)
0102     sdc1    $f28, THREAD_FPR28(\thread)
0103     sdc1    $f30, THREAD_FPR30(\thread)
0104     sw  \tmp, THREAD_FCR31(\thread)
0105     .set    pop
0106     .endm
0107 
0108     .macro  fpu_save_16odd thread
0109     .set    push
0110     .set    mips64r2
0111     .set    fp=64
0112     SET_HARDFLOAT
0113     sdc1    $f1,  THREAD_FPR1(\thread)
0114     sdc1    $f3,  THREAD_FPR3(\thread)
0115     sdc1    $f5,  THREAD_FPR5(\thread)
0116     sdc1    $f7,  THREAD_FPR7(\thread)
0117     sdc1    $f9,  THREAD_FPR9(\thread)
0118     sdc1    $f11, THREAD_FPR11(\thread)
0119     sdc1    $f13, THREAD_FPR13(\thread)
0120     sdc1    $f15, THREAD_FPR15(\thread)
0121     sdc1    $f17, THREAD_FPR17(\thread)
0122     sdc1    $f19, THREAD_FPR19(\thread)
0123     sdc1    $f21, THREAD_FPR21(\thread)
0124     sdc1    $f23, THREAD_FPR23(\thread)
0125     sdc1    $f25, THREAD_FPR25(\thread)
0126     sdc1    $f27, THREAD_FPR27(\thread)
0127     sdc1    $f29, THREAD_FPR29(\thread)
0128     sdc1    $f31, THREAD_FPR31(\thread)
0129     .set    pop
0130     .endm
0131 
0132     .macro  fpu_save_double thread status tmp
0133 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
0134     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
0135     sll \tmp, \status, 5
0136     bgez    \tmp, 10f
0137     fpu_save_16odd \thread
0138 10:
0139 #endif
0140     fpu_save_16even \thread \tmp
0141     .endm
0142 
0143     .macro  fpu_restore_16even thread tmp=t0
0144     .set    push
0145     SET_HARDFLOAT
0146     lw  \tmp, THREAD_FCR31(\thread)
0147     ldc1    $f0,  THREAD_FPR0(\thread)
0148     ldc1    $f2,  THREAD_FPR2(\thread)
0149     ldc1    $f4,  THREAD_FPR4(\thread)
0150     ldc1    $f6,  THREAD_FPR6(\thread)
0151     ldc1    $f8,  THREAD_FPR8(\thread)
0152     ldc1    $f10, THREAD_FPR10(\thread)
0153     ldc1    $f12, THREAD_FPR12(\thread)
0154     ldc1    $f14, THREAD_FPR14(\thread)
0155     ldc1    $f16, THREAD_FPR16(\thread)
0156     ldc1    $f18, THREAD_FPR18(\thread)
0157     ldc1    $f20, THREAD_FPR20(\thread)
0158     ldc1    $f22, THREAD_FPR22(\thread)
0159     ldc1    $f24, THREAD_FPR24(\thread)
0160     ldc1    $f26, THREAD_FPR26(\thread)
0161     ldc1    $f28, THREAD_FPR28(\thread)
0162     ldc1    $f30, THREAD_FPR30(\thread)
0163     ctc1    \tmp, fcr31
0164     .set    pop
0165     .endm
0166 
0167     .macro  fpu_restore_16odd thread
0168     .set    push
0169     .set    mips64r2
0170     .set    fp=64
0171     SET_HARDFLOAT
0172     ldc1    $f1,  THREAD_FPR1(\thread)
0173     ldc1    $f3,  THREAD_FPR3(\thread)
0174     ldc1    $f5,  THREAD_FPR5(\thread)
0175     ldc1    $f7,  THREAD_FPR7(\thread)
0176     ldc1    $f9,  THREAD_FPR9(\thread)
0177     ldc1    $f11, THREAD_FPR11(\thread)
0178     ldc1    $f13, THREAD_FPR13(\thread)
0179     ldc1    $f15, THREAD_FPR15(\thread)
0180     ldc1    $f17, THREAD_FPR17(\thread)
0181     ldc1    $f19, THREAD_FPR19(\thread)
0182     ldc1    $f21, THREAD_FPR21(\thread)
0183     ldc1    $f23, THREAD_FPR23(\thread)
0184     ldc1    $f25, THREAD_FPR25(\thread)
0185     ldc1    $f27, THREAD_FPR27(\thread)
0186     ldc1    $f29, THREAD_FPR29(\thread)
0187     ldc1    $f31, THREAD_FPR31(\thread)
0188     .set    pop
0189     .endm
0190 
0191     .macro  fpu_restore_double thread status tmp
0192 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
0193     defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
0194     sll \tmp, \status, 5
0195     bgez    \tmp, 10f               # 16 register mode?
0196 
0197     fpu_restore_16odd \thread
0198 10:
0199 #endif
0200     fpu_restore_16even \thread \tmp
0201     .endm
0202 
0203 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
0204     defined(CONFIG_CPU_MIPSR6)
0205     .macro  _EXT    rd, rs, p, s
0206     ext \rd, \rs, \p, \s
0207     .endm
0208 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
0209     .macro  _EXT    rd, rs, p, s
0210     srl \rd, \rs, \p
0211     andi    \rd, \rd, (1 << \s) - 1
0212     .endm
0213 #endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
0214 
0215 /*
0216  * Temporary until all gas have MT ASE support
0217  */
0218     .macro  DMT reg=0
0219     .word   0x41600bc1 | (\reg << 16)
0220     .endm
0221 
0222     .macro  EMT reg=0
0223     .word   0x41600be1 | (\reg << 16)
0224     .endm
0225 
0226     .macro  DVPE    reg=0
0227     .word   0x41600001 | (\reg << 16)
0228     .endm
0229 
0230     .macro  EVPE    reg=0
0231     .word   0x41600021 | (\reg << 16)
0232     .endm
0233 
0234     .macro  MFTR    rt=0, rd=0, u=0, sel=0
0235      .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
0236     .endm
0237 
0238     .macro  MTTR    rt=0, rd=0, u=0, sel=0
0239      .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
0240     .endm
0241 
0242 #ifdef TOOLCHAIN_SUPPORTS_MSA
0243     .macro  _cfcmsa rd, cs
0244     .set    push
0245     .set    mips32r2
0246     .set    fp=64
0247     .set    msa
0248     cfcmsa  \rd, $\cs
0249     .set    pop
0250     .endm
0251 
0252     .macro  _ctcmsa cd, rs
0253     .set    push
0254     .set    mips32r2
0255     .set    fp=64
0256     .set    msa
0257     ctcmsa  $\cd, \rs
0258     .set    pop
0259     .endm
0260 
0261     .macro  ld_b    wd, off, base
0262     .set    push
0263     .set    mips32r2
0264     .set    fp=64
0265     .set    msa
0266     ld.b    $w\wd, \off(\base)
0267     .set    pop
0268     .endm
0269 
0270     .macro  ld_h    wd, off, base
0271     .set    push
0272     .set    mips32r2
0273     .set    fp=64
0274     .set    msa
0275     ld.h    $w\wd, \off(\base)
0276     .set    pop
0277     .endm
0278 
0279     .macro  ld_w    wd, off, base
0280     .set    push
0281     .set    mips32r2
0282     .set    fp=64
0283     .set    msa
0284     ld.w    $w\wd, \off(\base)
0285     .set    pop
0286     .endm
0287 
0288     .macro  ld_d    wd, off, base
0289     .set    push
0290     .set    mips32r2
0291     .set    fp=64
0292     .set    msa
0293     ld.d    $w\wd, \off(\base)
0294     .set    pop
0295     .endm
0296 
0297     .macro  st_b    wd, off, base
0298     .set    push
0299     .set    mips32r2
0300     .set    fp=64
0301     .set    msa
0302     st.b    $w\wd, \off(\base)
0303     .set    pop
0304     .endm
0305 
0306     .macro  st_h    wd, off, base
0307     .set    push
0308     .set    mips32r2
0309     .set    fp=64
0310     .set    msa
0311     st.h    $w\wd, \off(\base)
0312     .set    pop
0313     .endm
0314 
0315     .macro  st_w    wd, off, base
0316     .set    push
0317     .set    mips32r2
0318     .set    fp=64
0319     .set    msa
0320     st.w    $w\wd, \off(\base)
0321     .set    pop
0322     .endm
0323 
0324     .macro  st_d    wd, off, base
0325     .set    push
0326     .set    mips32r2
0327     .set    fp=64
0328     .set    msa
0329     st.d    $w\wd, \off(\base)
0330     .set    pop
0331     .endm
0332 
0333     .macro  copy_s_w    ws, n
0334     .set    push
0335     .set    mips32r2
0336     .set    fp=64
0337     .set    msa
0338     copy_s.w $1, $w\ws[\n]
0339     .set    pop
0340     .endm
0341 
0342     .macro  copy_s_d    ws, n
0343     .set    push
0344     .set    mips64r2
0345     .set    fp=64
0346     .set    msa
0347     copy_s.d $1, $w\ws[\n]
0348     .set    pop
0349     .endm
0350 
0351     .macro  insert_w    wd, n
0352     .set    push
0353     .set    mips32r2
0354     .set    fp=64
0355     .set    msa
0356     insert.w $w\wd[\n], $1
0357     .set    pop
0358     .endm
0359 
0360     .macro  insert_d    wd, n
0361     .set    push
0362     .set    mips64r2
0363     .set    fp=64
0364     .set    msa
0365     insert.d $w\wd[\n], $1
0366     .set    pop
0367     .endm
0368 #else
0369 
0370     /*
0371      * Temporary until all toolchains in use include MSA support.
0372      */
0373     .macro  _cfcmsa rd, cs
0374     .set    push
0375     .set    noat
0376     SET_HARDFLOAT
0377     insn_if_mips 0x787e0059 | (\cs << 11)
0378     insn32_if_mm 0x587e0056 | (\cs << 11)
0379     move    \rd, $1
0380     .set    pop
0381     .endm
0382 
0383     .macro  _ctcmsa cd, rs
0384     .set    push
0385     .set    noat
0386     SET_HARDFLOAT
0387     move    $1, \rs
0388     insn_if_mips 0x783e0819 | (\cd << 6)
0389     insn32_if_mm 0x583e0816 | (\cd << 6)
0390     .set    pop
0391     .endm
0392 
0393     .macro  ld_b    wd, off, base
0394     .set    push
0395     .set    noat
0396     SET_HARDFLOAT
0397     PTR_ADDU $1, \base, \off
0398     insn_if_mips 0x78000820 | (\wd << 6)
0399     insn32_if_mm 0x58000807 | (\wd << 6)
0400     .set    pop
0401     .endm
0402 
0403     .macro  ld_h    wd, off, base
0404     .set    push
0405     .set    noat
0406     SET_HARDFLOAT
0407     PTR_ADDU $1, \base, \off
0408     insn_if_mips 0x78000821 | (\wd << 6)
0409     insn32_if_mm 0x58000817 | (\wd << 6)
0410     .set    pop
0411     .endm
0412 
0413     .macro  ld_w    wd, off, base
0414     .set    push
0415     .set    noat
0416     SET_HARDFLOAT
0417     PTR_ADDU $1, \base, \off
0418     insn_if_mips 0x78000822 | (\wd << 6)
0419     insn32_if_mm 0x58000827 | (\wd << 6)
0420     .set    pop
0421     .endm
0422 
0423     .macro  ld_d    wd, off, base
0424     .set    push
0425     .set    noat
0426     SET_HARDFLOAT
0427     PTR_ADDU $1, \base, \off
0428     insn_if_mips 0x78000823 | (\wd << 6)
0429     insn32_if_mm 0x58000837 | (\wd << 6)
0430     .set    pop
0431     .endm
0432 
0433     .macro  st_b    wd, off, base
0434     .set    push
0435     .set    noat
0436     SET_HARDFLOAT
0437     PTR_ADDU $1, \base, \off
0438     insn_if_mips 0x78000824 | (\wd << 6)
0439     insn32_if_mm 0x5800080f | (\wd << 6)
0440     .set    pop
0441     .endm
0442 
0443     .macro  st_h    wd, off, base
0444     .set    push
0445     .set    noat
0446     SET_HARDFLOAT
0447     PTR_ADDU $1, \base, \off
0448     insn_if_mips 0x78000825 | (\wd << 6)
0449     insn32_if_mm 0x5800081f | (\wd << 6)
0450     .set    pop
0451     .endm
0452 
0453     .macro  st_w    wd, off, base
0454     .set    push
0455     .set    noat
0456     SET_HARDFLOAT
0457     PTR_ADDU $1, \base, \off
0458     insn_if_mips 0x78000826 | (\wd << 6)
0459     insn32_if_mm 0x5800082f | (\wd << 6)
0460     .set    pop
0461     .endm
0462 
0463     .macro  st_d    wd, off, base
0464     .set    push
0465     .set    noat
0466     SET_HARDFLOAT
0467     PTR_ADDU $1, \base, \off
0468     insn_if_mips 0x78000827 | (\wd << 6)
0469     insn32_if_mm 0x5800083f | (\wd << 6)
0470     .set    pop
0471     .endm
0472 
0473     .macro  copy_s_w    ws, n
0474     .set    push
0475     .set    noat
0476     SET_HARDFLOAT
0477     insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
0478     insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
0479     .set    pop
0480     .endm
0481 
0482     .macro  copy_s_d    ws, n
0483     .set    push
0484     .set    noat
0485     SET_HARDFLOAT
0486     insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
0487     insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
0488     .set    pop
0489     .endm
0490 
0491     .macro  insert_w    wd, n
0492     .set    push
0493     .set    noat
0494     SET_HARDFLOAT
0495     insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
0496     insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
0497     .set    pop
0498     .endm
0499 
0500     .macro  insert_d    wd, n
0501     .set    push
0502     .set    noat
0503     SET_HARDFLOAT
0504     insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
0505     insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
0506     .set    pop
0507     .endm
0508 #endif
0509 
0510 #ifdef TOOLCHAIN_SUPPORTS_MSA
0511 #define FPR_BASE_OFFS   THREAD_FPR0
0512 #define FPR_BASE    $1
0513 #else
0514 #define FPR_BASE_OFFS   0
0515 #define FPR_BASE    \thread
0516 #endif
0517 
0518     .macro  msa_save_all    thread
0519     .set    push
0520     .set    noat
0521 #ifdef TOOLCHAIN_SUPPORTS_MSA
0522     PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
0523 #endif
0524     st_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
0525     st_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
0526     st_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
0527     st_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
0528     st_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
0529     st_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
0530     st_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
0531     st_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
0532     st_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
0533     st_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
0534     st_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
0535     st_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
0536     st_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
0537     st_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
0538     st_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
0539     st_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
0540     st_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
0541     st_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
0542     st_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
0543     st_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
0544     st_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
0545     st_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
0546     st_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
0547     st_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
0548     st_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
0549     st_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
0550     st_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
0551     st_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
0552     st_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
0553     st_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
0554     st_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
0555     st_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
0556     SET_HARDFLOAT
0557     _cfcmsa $1, MSA_CSR
0558     sw  $1, THREAD_MSA_CSR(\thread)
0559     .set    pop
0560     .endm
0561 
0562     .macro  msa_restore_all thread
0563     .set    push
0564     .set    noat
0565     SET_HARDFLOAT
0566     lw  $1, THREAD_MSA_CSR(\thread)
0567     _ctcmsa MSA_CSR, $1
0568 #ifdef TOOLCHAIN_SUPPORTS_MSA
0569     PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
0570 #endif
0571     ld_d     0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
0572     ld_d     1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
0573     ld_d     2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
0574     ld_d     3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
0575     ld_d     4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
0576     ld_d     5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
0577     ld_d     6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
0578     ld_d     7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
0579     ld_d     8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
0580     ld_d     9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
0581     ld_d    10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
0582     ld_d    11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
0583     ld_d    12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
0584     ld_d    13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
0585     ld_d    14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
0586     ld_d    15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
0587     ld_d    16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
0588     ld_d    17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
0589     ld_d    18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
0590     ld_d    19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
0591     ld_d    20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
0592     ld_d    21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
0593     ld_d    22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
0594     ld_d    23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
0595     ld_d    24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
0596     ld_d    25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
0597     ld_d    26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
0598     ld_d    27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
0599     ld_d    28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
0600     ld_d    29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
0601     ld_d    30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
0602     ld_d    31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
0603     .set pop
0604     .endm
0605 
0606 #undef FPR_BASE_OFFS
0607 #undef FPR_BASE
0608 
0609     .macro  msa_init_upper wd
0610 #ifdef CONFIG_64BIT
0611     insert_d \wd, 1
0612 #else
0613     insert_w \wd, 2
0614     insert_w \wd, 3
0615 #endif
0616     .endm
0617 
0618     .macro  msa_init_all_upper
0619     .set    push
0620     .set    noat
0621     SET_HARDFLOAT
0622     not $1, zero
0623     msa_init_upper  0
0624     msa_init_upper  1
0625     msa_init_upper  2
0626     msa_init_upper  3
0627     msa_init_upper  4
0628     msa_init_upper  5
0629     msa_init_upper  6
0630     msa_init_upper  7
0631     msa_init_upper  8
0632     msa_init_upper  9
0633     msa_init_upper  10
0634     msa_init_upper  11
0635     msa_init_upper  12
0636     msa_init_upper  13
0637     msa_init_upper  14
0638     msa_init_upper  15
0639     msa_init_upper  16
0640     msa_init_upper  17
0641     msa_init_upper  18
0642     msa_init_upper  19
0643     msa_init_upper  20
0644     msa_init_upper  21
0645     msa_init_upper  22
0646     msa_init_upper  23
0647     msa_init_upper  24
0648     msa_init_upper  25
0649     msa_init_upper  26
0650     msa_init_upper  27
0651     msa_init_upper  28
0652     msa_init_upper  29
0653     msa_init_upper  30
0654     msa_init_upper  31
0655     .set    pop
0656     .endm
0657 
0658 #endif /* _ASM_ASMMACRO_H */
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