include/asm/asm.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
0007  * Copyright (C) 1999 by Silicon Graphics, Inc.
0008  * Copyright (C) 2001 MIPS Technologies, Inc.
0009  * Copyright (C) 2002  Maciej W. Rozycki
0010  *
0011  * Some useful macros for MIPS assembler code
0012  *
0013  * Some of the routines below contain useless nops that will be optimized
0014  * away by gas in -O mode. These nops are however required to fill delay
0015  * slots in noreorder mode.
0016  */
0017 #ifndef __ASM_ASM_H
0018 #define __ASM_ASM_H
0019
0020 #include <asm/sgidefs.h>
0021 #include <asm/asm-eva.h>
0022 #include <asm/isa-rev.h>
0023
0024 #ifndef __VDSO__
0025 /*
0026  * Emit CFI data in .debug_frame sections, not .eh_frame sections.
0027  * We don't do DWARF unwinding at runtime, so only the offline DWARF
0028  * information is useful to anyone. Note we should change this if we
0029  * ever decide to enable DWARF unwinding at runtime.
0030  */
0031 #define CFI_SECTIONS    .cfi_sections .debug_frame
0032 #else
0033  /*
0034   * For the vDSO, emit both runtime unwind information and debug
0035   * symbols for the .dbg file.
0036   */
0037 #define CFI_SECTIONS
0038 #endif
0039
0040 /*
0041  * LEAF - declare leaf routine
0042  */
0043 #define LEAF(symbol)                    \
0044         CFI_SECTIONS;               \
0045         .globl  symbol;             \
0046         .align  2;              \
0047         .type   symbol, @function;      \
0048         .ent    symbol, 0;          \
0049 symbol:     .frame  sp, 0, ra;          \
0050         .cfi_startproc;             \
0051         .insn
0052
0053 /*
0054  * NESTED - declare nested routine entry point
0055  */
0056 #define NESTED(symbol, framesize, rpc)          \
0057         CFI_SECTIONS;               \
0058         .globl  symbol;             \
0059         .align  2;              \
0060         .type   symbol, @function;      \
0061         .ent    symbol, 0;          \
0062 symbol:     .frame  sp, framesize, rpc;     \
0063         .cfi_startproc;             \
0064         .insn
0065
0066 /*
0067  * END - mark end of function
0068  */
0069 #define END(function)                   \
0070         .cfi_endproc;               \
0071         .end    function;           \
0072         .size   function, .-function
0073
0074 /*
0075  * EXPORT - export definition of symbol
0076  */
0077 #define EXPORT(symbol)                  \
0078         .globl  symbol;             \
0079 symbol:
0080
0081 /*
0082  * FEXPORT - export definition of a function symbol
0083  */
0084 #define FEXPORT(symbol)                 \
0085         .globl  symbol;             \
0086         .type   symbol, @function;      \
0087 symbol:     .insn
0088
0089 /*
0090  * ABS - export absolute symbol
0091  */
0092 #define ABS(symbol,value)               \
0093         .globl  symbol;             \
0094 symbol      =   value
0095
0096 #define TEXT(msg)                   \
0097         .pushsection .data;         \
0098 8:      .asciiz msg;                \
0099         .popsection;
0100
0101 #define ASM_PANIC(msg)                  \
0102         .set    push;               \
0103         .set    reorder;            \
0104         PTR_LA  a0, 8f;             \
0105         jal panic;              \
0106 9:      b   9b;             \
0107         .set    pop;                \
0108         TEXT(msg)
0109
0110 /*
0111  * Print formatted string
0112  */
0113 #ifdef CONFIG_PRINTK
0114 #define ASM_PRINT(string)               \
0115         .set    push;               \
0116         .set    reorder;            \
0117         PTR_LA  a0, 8f;             \
0118         jal _printk;            \
0119         .set    pop;                \
0120         TEXT(string)
0121 #else
0122 #define ASM_PRINT(string)
0123 #endif
0124
0125 /*
0126  * Stack alignment
0127  */
0128 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
0129 #define ALSZ    7
0130 #define ALMASK  ~7
0131 #endif
0132 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
0133 #define ALSZ    15
0134 #define ALMASK  ~15
0135 #endif
0136
0137 /*
0138  * Macros to handle different pointer/register sizes for 32/64-bit code
0139  */
0140
0141 /*
0142  * Size of a register
0143  */
0144 #ifdef __mips64
0145 #define SZREG   8
0146 #else
0147 #define SZREG   4
0148 #endif
0149
0150 /*
0151  * Use the following macros in assemblercode to load/store registers,
0152  * pointers etc.
0153  */
0154 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
0155 #define REG_S       sw
0156 #define REG_L       lw
0157 #define REG_SUBU    subu
0158 #define REG_ADDU    addu
0159 #endif
0160 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
0161 #define REG_S       sd
0162 #define REG_L       ld
0163 #define REG_SUBU    dsubu
0164 #define REG_ADDU    daddu
0165 #endif
0166
0167 /*
0168  * How to add/sub/load/store/shift C int variables.
0169  */
0170 #if (_MIPS_SZINT == 32)
0171 #define INT_ADD     add
0172 #define INT_ADDU    addu
0173 #define INT_ADDI    addi
0174 #define INT_ADDIU   addiu
0175 #define INT_SUB     sub
0176 #define INT_SUBU    subu
0177 #define INT_L       lw
0178 #define INT_S       sw
0179 #define INT_SLL     sll
0180 #define INT_SLLV    sllv
0181 #define INT_SRL     srl
0182 #define INT_SRLV    srlv
0183 #define INT_SRA     sra
0184 #define INT_SRAV    srav
0185 #endif
0186
0187 #if (_MIPS_SZINT == 64)
0188 #define INT_ADD     dadd
0189 #define INT_ADDU    daddu
0190 #define INT_ADDI    daddi
0191 #define INT_ADDIU   daddiu
0192 #define INT_SUB     dsub
0193 #define INT_SUBU    dsubu
0194 #define INT_L       ld
0195 #define INT_S       sd
0196 #define INT_SLL     dsll
0197 #define INT_SLLV    dsllv
0198 #define INT_SRL     dsrl
0199 #define INT_SRLV    dsrlv
0200 #define INT_SRA     dsra
0201 #define INT_SRAV    dsrav
0202 #endif
0203
0204 /*
0205  * How to add/sub/load/store/shift C long variables.
0206  */
0207 #if (_MIPS_SZLONG == 32)
0208 #define LONG_ADD    add
0209 #define LONG_ADDU   addu
0210 #define LONG_ADDI   addi
0211 #define LONG_ADDIU  addiu
0212 #define LONG_SUB    sub
0213 #define LONG_SUBU   subu
0214 #define LONG_L      lw
0215 #define LONG_LL     ll
0216 #define LONG_SC     sc
0217 #define LONG_S      sw
0218 #define LONG_SP     swp
0219 #define LONG_SLL    sll
0220 #define LONG_SLLV   sllv
0221 #define LONG_SRL    srl
0222 #define LONG_SRLV   srlv
0223 #define LONG_SRA    sra
0224 #define LONG_SRAV   srav
0225 #define LONG_INS    ins
0226 #define LONG_EXT    ext
0227
0228 #ifdef __ASSEMBLY__
0229 #define LONG        .word
0230 #endif
0231 #define LONGSIZE    4
0232 #define LONGMASK    3
0233 #define LONGLOG     2
0234 #endif
0235
0236 #if (_MIPS_SZLONG == 64)
0237 #define LONG_ADD    dadd
0238 #define LONG_ADDU   daddu
0239 #define LONG_ADDI   daddi
0240 #define LONG_ADDIU  daddiu
0241 #define LONG_SUB    dsub
0242 #define LONG_SUBU   dsubu
0243 #define LONG_L      ld
0244 #define LONG_LL     lld
0245 #define LONG_SC     scd
0246 #define LONG_S      sd
0247 #define LONG_SP     sdp
0248 #define LONG_SLL    dsll
0249 #define LONG_SLLV   dsllv
0250 #define LONG_SRL    dsrl
0251 #define LONG_SRLV   dsrlv
0252 #define LONG_SRA    dsra
0253 #define LONG_SRAV   dsrav
0254 #define LONG_INS    dins
0255 #define LONG_EXT    dext
0256
0257 #ifdef __ASSEMBLY__
0258 #define LONG        .dword
0259 #endif
0260 #define LONGSIZE    8
0261 #define LONGMASK    7
0262 #define LONGLOG     3
0263 #endif
0264
0265 /*
0266  * How to add/sub/load/store/shift pointers.
0267  */
0268 #if (_MIPS_SZPTR == 32)
0269 #define PTR_ADD     add
0270 #define PTR_ADDU    addu
0271 #define PTR_ADDI    addi
0272 #define PTR_ADDIU   addiu
0273 #define PTR_SUB     sub
0274 #define PTR_SUBU    subu
0275 #define PTR_L       lw
0276 #define PTR_S       sw
0277 #define PTR_LA      la
0278 #define PTR_LI      li
0279 #define PTR_SLL     sll
0280 #define PTR_SLLV    sllv
0281 #define PTR_SRL     srl
0282 #define PTR_SRLV    srlv
0283 #define PTR_SRA     sra
0284 #define PTR_SRAV    srav
0285
0286 #define PTR_SCALESHIFT  2
0287
0288 #define PTR_WD      .word
0289 #define PTRSIZE     4
0290 #define PTRLOG      2
0291 #endif
0292
0293 #if (_MIPS_SZPTR == 64)
0294 #define PTR_ADD     dadd
0295 #define PTR_ADDU    daddu
0296 #define PTR_ADDI    daddi
0297 #define PTR_ADDIU   daddiu
0298 #define PTR_SUB     dsub
0299 #define PTR_SUBU    dsubu
0300 #define PTR_L       ld
0301 #define PTR_S       sd
0302 #define PTR_LA      dla
0303 #define PTR_LI      dli
0304 #define PTR_SLL     dsll
0305 #define PTR_SLLV    dsllv
0306 #define PTR_SRL     dsrl
0307 #define PTR_SRLV    dsrlv
0308 #define PTR_SRA     dsra
0309 #define PTR_SRAV    dsrav
0310
0311 #define PTR_SCALESHIFT  3
0312
0313 #define PTR_WD      .dword
0314 #define PTRSIZE     8
0315 #define PTRLOG      3
0316 #endif
0317
0318 /*
0319  * Some cp0 registers were extended to 64bit for MIPS III.
0320  */
0321 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
0322 #define MFC0        mfc0
0323 #define MTC0        mtc0
0324 #endif
0325 #if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
0326 #define MFC0        dmfc0
0327 #define MTC0        dmtc0
0328 #endif
0329
0330 #define SSNOP       sll zero, zero, 1
0331
0332 /*
0333  * Using a branch-likely instruction to check the result of an sc instruction
0334  * works around a bug present in R10000 CPUs prior to revision 3.0 that could
0335  * cause ll-sc sequences to execute non-atomically.
0336  */
0337 #ifdef CONFIG_WAR_R10000_LLSC
0338 # define SC_BEQZ    beqzl
0339 #elif MIPS_ISA_REV >= 6
0340 # define SC_BEQZ    beqzc
0341 #else
0342 # define SC_BEQZ    beqz
0343 #endif
0344
0345 #ifdef CONFIG_SGI_IP28
0346 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
0347 #include <asm/cacheops.h>
0348 #define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
0349 #else
0350 #define R10KCBARRIER(addr)
0351 #endif
0352
0353 #endif /* __ASM_ASM_H */