fw/arc/promlib.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
0007  * Compatibility with board caches, Ulf Carlsson
0008  */
0009 #include <linux/kernel.h>
0010 #include <asm/sgialib.h>
0011 #include <asm/bcache.h>
0012 #include <asm/setup.h>
0013
0014 #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
0015 /*
0016  * For 64bit kernels working with a 32bit ARC PROM pointer arguments
0017  * for ARC calls need to reside in CKEG0/1. But as soon as the kernel
0018  * switches to it's first kernel thread stack is set to an address in
0019  * XKPHYS, so anything on stack can't be used anymore. This is solved
0020  * by using a * static declartion variables are put into BSS, which is
0021  * linked to a CKSEG0 address. Since this is only used on UP platforms
0022  * there is not spinlock needed
0023  */
0024 #define O32_STATIC  static
0025 #else
0026 #define O32_STATIC
0027 #endif
0028
0029 /*
0030  * IP22 boardcache is not compatible with board caches.  Thus we disable it
0031  * during romvec action.  Since r4xx0.c is always compiled and linked with your
0032  * kernel, this shouldn't cause any harm regardless what MIPS processor you
0033  * have.
0034  *
0035  * The ARC write and read functions seem to interfere with the serial lines
0036  * in some way. You should be careful with them.
0037  */
0038
0039 void prom_putchar(char c)
0040 {
0041     O32_STATIC ULONG cnt;
0042     O32_STATIC CHAR it;
0043
0044     it = c;
0045
0046     bc_disable();
0047     ArcWrite(1, &it, 1, &cnt);
0048     bc_enable();
0049 }
0050
0051 char prom_getchar(void)
0052 {
0053     O32_STATIC ULONG cnt;
0054     O32_STATIC CHAR c;
0055
0056     bc_disable();
0057     ArcRead(0, &c, 1, &cnt);
0058     bc_enable();
0059
0060     return c;
0061 }