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OSCL-LXR
 
 

     

0001 /*
0002  * System-specific setup, especially interrupts.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 1998 Harald Koerfgen
0009  * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020  Maciej W. Rozycki
0010  */
0011 #include <linux/console.h>
0012 #include <linux/export.h>
0013 #include <linux/init.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/ioport.h>
0016 #include <linux/irq.h>
0017 #include <linux/irqnr.h>
0018 #include <linux/memblock.h>
0019 #include <linux/param.h>
0020 #include <linux/percpu-defs.h>
0021 #include <linux/sched.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/types.h>
0024 #include <linux/pm.h>
0025 
0026 #include <asm/addrspace.h>
0027 #include <asm/bootinfo.h>
0028 #include <asm/cpu.h>
0029 #include <asm/cpu-features.h>
0030 #include <asm/cpu-type.h>
0031 #include <asm/irq.h>
0032 #include <asm/irq_cpu.h>
0033 #include <asm/mipsregs.h>
0034 #include <asm/page.h>
0035 #include <asm/reboot.h>
0036 #include <asm/sections.h>
0037 #include <asm/time.h>
0038 #include <asm/traps.h>
0039 #include <asm/wbflush.h>
0040 
0041 #include <asm/dec/interrupts.h>
0042 #include <asm/dec/ioasic.h>
0043 #include <asm/dec/ioasic_addrs.h>
0044 #include <asm/dec/ioasic_ints.h>
0045 #include <asm/dec/kn01.h>
0046 #include <asm/dec/kn02.h>
0047 #include <asm/dec/kn02ba.h>
0048 #include <asm/dec/kn02ca.h>
0049 #include <asm/dec/kn03.h>
0050 #include <asm/dec/kn230.h>
0051 #include <asm/dec/system.h>
0052 
0053 
0054 extern void dec_machine_restart(char *command);
0055 extern void dec_machine_halt(void);
0056 extern void dec_machine_power_off(void);
0057 extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
0058 
0059 unsigned long dec_kn_slot_base, dec_kn_slot_size;
0060 
0061 EXPORT_SYMBOL(dec_kn_slot_base);
0062 EXPORT_SYMBOL(dec_kn_slot_size);
0063 
0064 int dec_tc_bus;
0065 
0066 DEFINE_SPINLOCK(ioasic_ssr_lock);
0067 EXPORT_SYMBOL(ioasic_ssr_lock);
0068 
0069 volatile u32 *ioasic_base;
0070 
0071 EXPORT_SYMBOL(ioasic_base);
0072 
0073 /*
0074  * IRQ routing and priority tables.  Priorities are set as follows:
0075  *
0076  *      KN01    KN230   KN02    KN02-BA KN02-CA KN03
0077  *
0078  * MEMORY   CPU CPU CPU ASIC    CPU CPU
0079  * RTC      CPU CPU CPU ASIC    CPU CPU
0080  * DMA      -   -   -   ASIC    ASIC    ASIC
0081  * SERIAL0  CPU CPU CSR ASIC    ASIC    ASIC
0082  * SERIAL1  -   -   -   ASIC    -   ASIC
0083  * SCSI     CPU CPU CSR ASIC    ASIC    ASIC
0084  * ETHERNET CPU *   CSR ASIC    ASIC    ASIC
0085  * other    -   -   -   ASIC    -   -
0086  * TC2      -   -   CSR CPU ASIC    ASIC
0087  * TC1      -   -   CSR CPU ASIC    ASIC
0088  * TC0      -   -   CSR CPU ASIC    ASIC
0089  * other    -   CPU -   CPU ASIC    ASIC
0090  * other    -   -   -   -   CPU CPU
0091  *
0092  * * -- shared with SCSI
0093  */
0094 
0095 int dec_interrupt[DEC_NR_INTS] = {
0096     [0 ... DEC_NR_INTS - 1] = -1
0097 };
0098 
0099 EXPORT_SYMBOL(dec_interrupt);
0100 
0101 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
0102     { { .i = ~0 }, { .p = dec_intr_unimplemented } },
0103 };
0104 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
0105     { { .i = ~0 }, { .p = asic_intr_unimplemented } },
0106 };
0107 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
0108 int *fpu_kstat_irq;
0109 
0110 static irq_handler_t busirq_handler;
0111 static unsigned int busirq_flags = IRQF_NO_THREAD;
0112 
0113 /*
0114  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
0115  */
0116 static void __init dec_be_init(void)
0117 {
0118     switch (mips_machtype) {
0119     case MACH_DS23100:  /* DS2100/DS3100 Pmin/Pmax */
0120         mips_set_be_handler(dec_kn01_be_handler);
0121         busirq_handler = dec_kn01_be_interrupt;
0122         busirq_flags |= IRQF_SHARED;
0123         dec_kn01_be_init();
0124         break;
0125     case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
0126     case MACH_DS5000_XX:    /* DS5000/xx Maxine */
0127         mips_set_be_handler(dec_kn02xa_be_handler);
0128         busirq_handler = dec_kn02xa_be_interrupt;
0129         dec_kn02xa_be_init();
0130         break;
0131     case MACH_DS5000_200:   /* DS5000/200 3max */
0132     case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
0133     case MACH_DS5900:   /* DS5900 bigmax */
0134         mips_set_be_handler(dec_ecc_be_handler);
0135         busirq_handler = dec_ecc_be_interrupt;
0136         dec_ecc_be_init();
0137         break;
0138     }
0139 }
0140 
0141 void __init plat_mem_setup(void)
0142 {
0143     board_be_init = dec_be_init;
0144 
0145     wbflush_setup();
0146 
0147     _machine_restart = dec_machine_restart;
0148     _machine_halt = dec_machine_halt;
0149     pm_power_off = dec_machine_power_off;
0150 
0151     ioport_resource.start = ~0UL;
0152     ioport_resource.end = 0UL;
0153 
0154     /* Stay away from the firmware working memory area for now. */
0155     memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET);
0156 }
0157 
0158 /*
0159  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
0160  * or DS3100 (aka Pmax).
0161  */
0162 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
0163     [DEC_IRQ_CASCADE]   = -1,
0164     [DEC_IRQ_AB_RECV]   = -1,
0165     [DEC_IRQ_AB_XMIT]   = -1,
0166     [DEC_IRQ_DZ11]      = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
0167     [DEC_IRQ_ASC]       = -1,
0168     [DEC_IRQ_FLOPPY]    = -1,
0169     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0170     [DEC_IRQ_HALT]      = -1,
0171     [DEC_IRQ_ISDN]      = -1,
0172     [DEC_IRQ_LANCE]     = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
0173     [DEC_IRQ_BUS]       = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
0174     [DEC_IRQ_PSU]       = -1,
0175     [DEC_IRQ_RTC]       = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
0176     [DEC_IRQ_SCC0]      = -1,
0177     [DEC_IRQ_SCC1]      = -1,
0178     [DEC_IRQ_SII]       = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
0179     [DEC_IRQ_TC0]       = -1,
0180     [DEC_IRQ_TC1]       = -1,
0181     [DEC_IRQ_TC2]       = -1,
0182     [DEC_IRQ_TIMER]     = -1,
0183     [DEC_IRQ_VIDEO]     = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
0184     [DEC_IRQ_ASC_MERR]  = -1,
0185     [DEC_IRQ_ASC_ERR]   = -1,
0186     [DEC_IRQ_ASC_DMA]   = -1,
0187     [DEC_IRQ_FLOPPY_ERR]    = -1,
0188     [DEC_IRQ_ISDN_ERR]  = -1,
0189     [DEC_IRQ_ISDN_RXDMA]    = -1,
0190     [DEC_IRQ_ISDN_TXDMA]    = -1,
0191     [DEC_IRQ_LANCE_MERR]    = -1,
0192     [DEC_IRQ_SCC0A_RXERR]   = -1,
0193     [DEC_IRQ_SCC0A_RXDMA]   = -1,
0194     [DEC_IRQ_SCC0A_TXERR]   = -1,
0195     [DEC_IRQ_SCC0A_TXDMA]   = -1,
0196     [DEC_IRQ_AB_RXERR]  = -1,
0197     [DEC_IRQ_AB_RXDMA]  = -1,
0198     [DEC_IRQ_AB_TXERR]  = -1,
0199     [DEC_IRQ_AB_TXDMA]  = -1,
0200     [DEC_IRQ_SCC1A_RXERR]   = -1,
0201     [DEC_IRQ_SCC1A_RXDMA]   = -1,
0202     [DEC_IRQ_SCC1A_TXERR]   = -1,
0203     [DEC_IRQ_SCC1A_TXDMA]   = -1,
0204 };
0205 
0206 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
0207     { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
0208         { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
0209     { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
0210         { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
0211     { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
0212         { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
0213     { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
0214         { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
0215     { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
0216         { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
0217     { { .i = DEC_CPU_IRQ_ALL },
0218         { .p = cpu_all_int } },
0219 };
0220 
0221 static void __init dec_init_kn01(void)
0222 {
0223     /* IRQ routing. */
0224     memcpy(&dec_interrupt, &kn01_interrupt,
0225         sizeof(kn01_interrupt));
0226 
0227     /* CPU IRQ priorities. */
0228     memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
0229         sizeof(kn01_cpu_mask_nr_tbl));
0230 
0231     mips_cpu_irq_init();
0232 
0233 }               /* dec_init_kn01 */
0234 
0235 
0236 /*
0237  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
0238  */
0239 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
0240     [DEC_IRQ_CASCADE]   = -1,
0241     [DEC_IRQ_AB_RECV]   = -1,
0242     [DEC_IRQ_AB_XMIT]   = -1,
0243     [DEC_IRQ_DZ11]      = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
0244     [DEC_IRQ_ASC]       = -1,
0245     [DEC_IRQ_FLOPPY]    = -1,
0246     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0247     [DEC_IRQ_HALT]      = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
0248     [DEC_IRQ_ISDN]      = -1,
0249     [DEC_IRQ_LANCE]     = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
0250     [DEC_IRQ_BUS]       = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
0251     [DEC_IRQ_PSU]       = -1,
0252     [DEC_IRQ_RTC]       = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
0253     [DEC_IRQ_SCC0]      = -1,
0254     [DEC_IRQ_SCC1]      = -1,
0255     [DEC_IRQ_SII]       = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
0256     [DEC_IRQ_TC0]       = -1,
0257     [DEC_IRQ_TC1]       = -1,
0258     [DEC_IRQ_TC2]       = -1,
0259     [DEC_IRQ_TIMER]     = -1,
0260     [DEC_IRQ_VIDEO]     = -1,
0261     [DEC_IRQ_ASC_MERR]  = -1,
0262     [DEC_IRQ_ASC_ERR]   = -1,
0263     [DEC_IRQ_ASC_DMA]   = -1,
0264     [DEC_IRQ_FLOPPY_ERR]    = -1,
0265     [DEC_IRQ_ISDN_ERR]  = -1,
0266     [DEC_IRQ_ISDN_RXDMA]    = -1,
0267     [DEC_IRQ_ISDN_TXDMA]    = -1,
0268     [DEC_IRQ_LANCE_MERR]    = -1,
0269     [DEC_IRQ_SCC0A_RXERR]   = -1,
0270     [DEC_IRQ_SCC0A_RXDMA]   = -1,
0271     [DEC_IRQ_SCC0A_TXERR]   = -1,
0272     [DEC_IRQ_SCC0A_TXDMA]   = -1,
0273     [DEC_IRQ_AB_RXERR]  = -1,
0274     [DEC_IRQ_AB_RXDMA]  = -1,
0275     [DEC_IRQ_AB_TXERR]  = -1,
0276     [DEC_IRQ_AB_TXDMA]  = -1,
0277     [DEC_IRQ_SCC1A_RXERR]   = -1,
0278     [DEC_IRQ_SCC1A_RXDMA]   = -1,
0279     [DEC_IRQ_SCC1A_TXERR]   = -1,
0280     [DEC_IRQ_SCC1A_TXDMA]   = -1,
0281 };
0282 
0283 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
0284     { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
0285         { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
0286     { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
0287         { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
0288     { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
0289         { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
0290     { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
0291         { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
0292     { { .i = DEC_CPU_IRQ_ALL },
0293         { .p = cpu_all_int } },
0294 };
0295 
0296 static void __init dec_init_kn230(void)
0297 {
0298     /* IRQ routing. */
0299     memcpy(&dec_interrupt, &kn230_interrupt,
0300         sizeof(kn230_interrupt));
0301 
0302     /* CPU IRQ priorities. */
0303     memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
0304         sizeof(kn230_cpu_mask_nr_tbl));
0305 
0306     mips_cpu_irq_init();
0307 
0308 }               /* dec_init_kn230 */
0309 
0310 
0311 /*
0312  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
0313  */
0314 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
0315     [DEC_IRQ_CASCADE]   = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
0316     [DEC_IRQ_AB_RECV]   = -1,
0317     [DEC_IRQ_AB_XMIT]   = -1,
0318     [DEC_IRQ_DZ11]      = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
0319     [DEC_IRQ_ASC]       = KN02_IRQ_NR(KN02_CSR_INR_ASC),
0320     [DEC_IRQ_FLOPPY]    = -1,
0321     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0322     [DEC_IRQ_HALT]      = -1,
0323     [DEC_IRQ_ISDN]      = -1,
0324     [DEC_IRQ_LANCE]     = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
0325     [DEC_IRQ_BUS]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
0326     [DEC_IRQ_PSU]       = -1,
0327     [DEC_IRQ_RTC]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
0328     [DEC_IRQ_SCC0]      = -1,
0329     [DEC_IRQ_SCC1]      = -1,
0330     [DEC_IRQ_SII]       = -1,
0331     [DEC_IRQ_TC0]       = KN02_IRQ_NR(KN02_CSR_INR_TC0),
0332     [DEC_IRQ_TC1]       = KN02_IRQ_NR(KN02_CSR_INR_TC1),
0333     [DEC_IRQ_TC2]       = KN02_IRQ_NR(KN02_CSR_INR_TC2),
0334     [DEC_IRQ_TIMER]     = -1,
0335     [DEC_IRQ_VIDEO]     = -1,
0336     [DEC_IRQ_ASC_MERR]  = -1,
0337     [DEC_IRQ_ASC_ERR]   = -1,
0338     [DEC_IRQ_ASC_DMA]   = -1,
0339     [DEC_IRQ_FLOPPY_ERR]    = -1,
0340     [DEC_IRQ_ISDN_ERR]  = -1,
0341     [DEC_IRQ_ISDN_RXDMA]    = -1,
0342     [DEC_IRQ_ISDN_TXDMA]    = -1,
0343     [DEC_IRQ_LANCE_MERR]    = -1,
0344     [DEC_IRQ_SCC0A_RXERR]   = -1,
0345     [DEC_IRQ_SCC0A_RXDMA]   = -1,
0346     [DEC_IRQ_SCC0A_TXERR]   = -1,
0347     [DEC_IRQ_SCC0A_TXDMA]   = -1,
0348     [DEC_IRQ_AB_RXERR]  = -1,
0349     [DEC_IRQ_AB_RXDMA]  = -1,
0350     [DEC_IRQ_AB_TXERR]  = -1,
0351     [DEC_IRQ_AB_TXDMA]  = -1,
0352     [DEC_IRQ_SCC1A_RXERR]   = -1,
0353     [DEC_IRQ_SCC1A_RXDMA]   = -1,
0354     [DEC_IRQ_SCC1A_TXERR]   = -1,
0355     [DEC_IRQ_SCC1A_TXDMA]   = -1,
0356 };
0357 
0358 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
0359     { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
0360         { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
0361     { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
0362         { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
0363     { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
0364         { .p = kn02_io_int } },
0365     { { .i = DEC_CPU_IRQ_ALL },
0366         { .p = cpu_all_int } },
0367 };
0368 
0369 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
0370     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
0371         { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
0372     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
0373         { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
0374     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
0375         { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
0376     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
0377         { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
0378     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
0379         { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
0380     { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
0381         { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
0382     { { .i = KN02_IRQ_ALL },
0383         { .p = kn02_all_int } },
0384 };
0385 
0386 static void __init dec_init_kn02(void)
0387 {
0388     /* IRQ routing. */
0389     memcpy(&dec_interrupt, &kn02_interrupt,
0390         sizeof(kn02_interrupt));
0391 
0392     /* CPU IRQ priorities. */
0393     memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
0394         sizeof(kn02_cpu_mask_nr_tbl));
0395 
0396     /* KN02 CSR IRQ priorities. */
0397     memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
0398         sizeof(kn02_asic_mask_nr_tbl));
0399 
0400     mips_cpu_irq_init();
0401     init_kn02_irqs(KN02_IRQ_BASE);
0402 
0403 }               /* dec_init_kn02 */
0404 
0405 
0406 /*
0407  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
0408  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
0409  * DS5000/150, aka 4min.
0410  */
0411 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
0412     [DEC_IRQ_CASCADE]   = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
0413     [DEC_IRQ_AB_RECV]   = -1,
0414     [DEC_IRQ_AB_XMIT]   = -1,
0415     [DEC_IRQ_DZ11]      = -1,
0416     [DEC_IRQ_ASC]       = IO_IRQ_NR(KN02BA_IO_INR_ASC),
0417     [DEC_IRQ_FLOPPY]    = -1,
0418     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0419     [DEC_IRQ_HALT]      = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
0420     [DEC_IRQ_ISDN]      = -1,
0421     [DEC_IRQ_LANCE]     = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
0422     [DEC_IRQ_BUS]       = IO_IRQ_NR(KN02BA_IO_INR_BUS),
0423     [DEC_IRQ_PSU]       = IO_IRQ_NR(KN02BA_IO_INR_PSU),
0424     [DEC_IRQ_RTC]       = IO_IRQ_NR(KN02BA_IO_INR_RTC),
0425     [DEC_IRQ_SCC0]      = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
0426     [DEC_IRQ_SCC1]      = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
0427     [DEC_IRQ_SII]       = -1,
0428     [DEC_IRQ_TC0]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
0429     [DEC_IRQ_TC1]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
0430     [DEC_IRQ_TC2]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
0431     [DEC_IRQ_TIMER]     = -1,
0432     [DEC_IRQ_VIDEO]     = -1,
0433     [DEC_IRQ_ASC_MERR]  = IO_IRQ_NR(IO_INR_ASC_MERR),
0434     [DEC_IRQ_ASC_ERR]   = IO_IRQ_NR(IO_INR_ASC_ERR),
0435     [DEC_IRQ_ASC_DMA]   = IO_IRQ_NR(IO_INR_ASC_DMA),
0436     [DEC_IRQ_FLOPPY_ERR]    = -1,
0437     [DEC_IRQ_ISDN_ERR]  = -1,
0438     [DEC_IRQ_ISDN_RXDMA]    = -1,
0439     [DEC_IRQ_ISDN_TXDMA]    = -1,
0440     [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
0441     [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
0442     [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
0443     [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
0444     [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
0445     [DEC_IRQ_AB_RXERR]  = -1,
0446     [DEC_IRQ_AB_RXDMA]  = -1,
0447     [DEC_IRQ_AB_TXERR]  = -1,
0448     [DEC_IRQ_AB_TXDMA]  = -1,
0449     [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
0450     [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
0451     [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
0452     [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
0453 };
0454 
0455 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
0456     { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
0457         { .p = kn02xa_io_int } },
0458     { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
0459         { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
0460     { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
0461         { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
0462     { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
0463         { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
0464     { { .i = DEC_CPU_IRQ_ALL },
0465         { .p = cpu_all_int } },
0466 };
0467 
0468 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
0469     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
0470         { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
0471     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
0472         { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
0473     { { .i = IO_IRQ_DMA },
0474         { .p = asic_dma_int } },
0475     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
0476         { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
0477     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
0478         { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
0479     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
0480         { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
0481     { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
0482         { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
0483     { { .i = IO_IRQ_ALL },
0484         { .p = asic_all_int } },
0485 };
0486 
0487 static void __init dec_init_kn02ba(void)
0488 {
0489     /* IRQ routing. */
0490     memcpy(&dec_interrupt, &kn02ba_interrupt,
0491         sizeof(kn02ba_interrupt));
0492 
0493     /* CPU IRQ priorities. */
0494     memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
0495         sizeof(kn02ba_cpu_mask_nr_tbl));
0496 
0497     /* I/O ASIC IRQ priorities. */
0498     memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
0499         sizeof(kn02ba_asic_mask_nr_tbl));
0500 
0501     mips_cpu_irq_init();
0502     init_ioasic_irqs(IO_IRQ_BASE);
0503 
0504 }               /* dec_init_kn02ba */
0505 
0506 
0507 /*
0508  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
0509  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
0510  * DS5000/50, aka 4MAXine.
0511  */
0512 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
0513     [DEC_IRQ_CASCADE]   = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
0514     [DEC_IRQ_AB_RECV]   = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
0515     [DEC_IRQ_AB_XMIT]   = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
0516     [DEC_IRQ_DZ11]      = -1,
0517     [DEC_IRQ_ASC]       = IO_IRQ_NR(KN02CA_IO_INR_ASC),
0518     [DEC_IRQ_FLOPPY]    = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
0519     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0520     [DEC_IRQ_HALT]      = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
0521     [DEC_IRQ_ISDN]      = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
0522     [DEC_IRQ_LANCE]     = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
0523     [DEC_IRQ_BUS]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
0524     [DEC_IRQ_PSU]       = -1,
0525     [DEC_IRQ_RTC]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
0526     [DEC_IRQ_SCC0]      = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
0527     [DEC_IRQ_SCC1]      = -1,
0528     [DEC_IRQ_SII]       = -1,
0529     [DEC_IRQ_TC0]       = IO_IRQ_NR(KN02CA_IO_INR_TC0),
0530     [DEC_IRQ_TC1]       = IO_IRQ_NR(KN02CA_IO_INR_TC1),
0531     [DEC_IRQ_TC2]       = -1,
0532     [DEC_IRQ_TIMER]     = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
0533     [DEC_IRQ_VIDEO]     = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
0534     [DEC_IRQ_ASC_MERR]  = IO_IRQ_NR(IO_INR_ASC_MERR),
0535     [DEC_IRQ_ASC_ERR]   = IO_IRQ_NR(IO_INR_ASC_ERR),
0536     [DEC_IRQ_ASC_DMA]   = IO_IRQ_NR(IO_INR_ASC_DMA),
0537     [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
0538     [DEC_IRQ_ISDN_ERR]  = IO_IRQ_NR(IO_INR_ISDN_ERR),
0539     [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
0540     [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
0541     [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
0542     [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
0543     [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
0544     [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
0545     [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
0546     [DEC_IRQ_AB_RXERR]  = IO_IRQ_NR(IO_INR_AB_RXERR),
0547     [DEC_IRQ_AB_RXDMA]  = IO_IRQ_NR(IO_INR_AB_RXDMA),
0548     [DEC_IRQ_AB_TXERR]  = IO_IRQ_NR(IO_INR_AB_TXERR),
0549     [DEC_IRQ_AB_TXDMA]  = IO_IRQ_NR(IO_INR_AB_TXDMA),
0550     [DEC_IRQ_SCC1A_RXERR]   = -1,
0551     [DEC_IRQ_SCC1A_RXDMA]   = -1,
0552     [DEC_IRQ_SCC1A_TXERR]   = -1,
0553     [DEC_IRQ_SCC1A_TXDMA]   = -1,
0554 };
0555 
0556 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
0557     { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
0558         { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
0559     { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
0560         { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
0561     { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
0562         { .p = kn02xa_io_int } },
0563     { { .i = DEC_CPU_IRQ_ALL },
0564         { .p = cpu_all_int } },
0565 };
0566 
0567 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
0568     { { .i = IO_IRQ_DMA },
0569         { .p = asic_dma_int } },
0570     { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
0571         { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
0572     { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
0573         { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
0574     { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
0575         { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
0576     { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
0577         { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
0578     { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
0579         { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
0580     { { .i = IO_IRQ_ALL },
0581         { .p = asic_all_int } },
0582 };
0583 
0584 static void __init dec_init_kn02ca(void)
0585 {
0586     /* IRQ routing. */
0587     memcpy(&dec_interrupt, &kn02ca_interrupt,
0588         sizeof(kn02ca_interrupt));
0589 
0590     /* CPU IRQ priorities. */
0591     memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
0592         sizeof(kn02ca_cpu_mask_nr_tbl));
0593 
0594     /* I/O ASIC IRQ priorities. */
0595     memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
0596         sizeof(kn02ca_asic_mask_nr_tbl));
0597 
0598     mips_cpu_irq_init();
0599     init_ioasic_irqs(IO_IRQ_BASE);
0600 
0601 }               /* dec_init_kn02ca */
0602 
0603 
0604 /*
0605  * Machine-specific initialisation for KN03, aka DS5000/240,
0606  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
0607  * DS5000/260, aka 4max+ and DS5900/260.
0608  */
0609 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
0610     [DEC_IRQ_CASCADE]   = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
0611     [DEC_IRQ_AB_RECV]   = -1,
0612     [DEC_IRQ_AB_XMIT]   = -1,
0613     [DEC_IRQ_DZ11]      = -1,
0614     [DEC_IRQ_ASC]       = IO_IRQ_NR(KN03_IO_INR_ASC),
0615     [DEC_IRQ_FLOPPY]    = -1,
0616     [DEC_IRQ_FPU]       = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
0617     [DEC_IRQ_HALT]      = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
0618     [DEC_IRQ_ISDN]      = -1,
0619     [DEC_IRQ_LANCE]     = IO_IRQ_NR(KN03_IO_INR_LANCE),
0620     [DEC_IRQ_BUS]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
0621     [DEC_IRQ_PSU]       = IO_IRQ_NR(KN03_IO_INR_PSU),
0622     [DEC_IRQ_RTC]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
0623     [DEC_IRQ_SCC0]      = IO_IRQ_NR(KN03_IO_INR_SCC0),
0624     [DEC_IRQ_SCC1]      = IO_IRQ_NR(KN03_IO_INR_SCC1),
0625     [DEC_IRQ_SII]       = -1,
0626     [DEC_IRQ_TC0]       = IO_IRQ_NR(KN03_IO_INR_TC0),
0627     [DEC_IRQ_TC1]       = IO_IRQ_NR(KN03_IO_INR_TC1),
0628     [DEC_IRQ_TC2]       = IO_IRQ_NR(KN03_IO_INR_TC2),
0629     [DEC_IRQ_TIMER]     = -1,
0630     [DEC_IRQ_VIDEO]     = -1,
0631     [DEC_IRQ_ASC_MERR]  = IO_IRQ_NR(IO_INR_ASC_MERR),
0632     [DEC_IRQ_ASC_ERR]   = IO_IRQ_NR(IO_INR_ASC_ERR),
0633     [DEC_IRQ_ASC_DMA]   = IO_IRQ_NR(IO_INR_ASC_DMA),
0634     [DEC_IRQ_FLOPPY_ERR]    = -1,
0635     [DEC_IRQ_ISDN_ERR]  = -1,
0636     [DEC_IRQ_ISDN_RXDMA]    = -1,
0637     [DEC_IRQ_ISDN_TXDMA]    = -1,
0638     [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
0639     [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
0640     [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
0641     [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
0642     [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
0643     [DEC_IRQ_AB_RXERR]  = -1,
0644     [DEC_IRQ_AB_RXDMA]  = -1,
0645     [DEC_IRQ_AB_TXERR]  = -1,
0646     [DEC_IRQ_AB_TXDMA]  = -1,
0647     [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
0648     [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
0649     [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
0650     [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
0651 };
0652 
0653 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
0654     { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
0655         { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
0656     { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
0657         { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
0658     { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
0659         { .p = kn03_io_int } },
0660     { { .i = DEC_CPU_IRQ_ALL },
0661         { .p = cpu_all_int } },
0662 };
0663 
0664 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
0665     { { .i = IO_IRQ_DMA },
0666         { .p = asic_dma_int } },
0667     { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
0668         { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
0669     { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
0670         { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
0671     { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
0672         { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
0673     { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
0674         { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
0675     { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
0676         { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
0677     { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
0678         { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
0679     { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
0680         { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
0681     { { .i = IO_IRQ_ALL },
0682         { .p = asic_all_int } },
0683 };
0684 
0685 static void __init dec_init_kn03(void)
0686 {
0687     /* IRQ routing. */
0688     memcpy(&dec_interrupt, &kn03_interrupt,
0689         sizeof(kn03_interrupt));
0690 
0691     /* CPU IRQ priorities. */
0692     memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
0693         sizeof(kn03_cpu_mask_nr_tbl));
0694 
0695     /* I/O ASIC IRQ priorities. */
0696     memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
0697         sizeof(kn03_asic_mask_nr_tbl));
0698 
0699     mips_cpu_irq_init();
0700     init_ioasic_irqs(IO_IRQ_BASE);
0701 
0702 }               /* dec_init_kn03 */
0703 
0704 
0705 void __init arch_init_irq(void)
0706 {
0707     switch (mips_machtype) {
0708     case MACH_DS23100:  /* DS2100/DS3100 Pmin/Pmax */
0709         dec_init_kn01();
0710         break;
0711     case MACH_DS5100:   /* DS5100 MIPSmate */
0712         dec_init_kn230();
0713         break;
0714     case MACH_DS5000_200:   /* DS5000/200 3max */
0715         dec_init_kn02();
0716         break;
0717     case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
0718         dec_init_kn02ba();
0719         break;
0720     case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
0721     case MACH_DS5900:   /* DS5900 bigmax */
0722         dec_init_kn03();
0723         break;
0724     case MACH_DS5000_XX:    /* Personal DS5000/xx */
0725         dec_init_kn02ca();
0726         break;
0727     case MACH_DS5800:   /* DS5800 Isis */
0728         panic("Don't know how to set this up!");
0729         break;
0730     case MACH_DS5400:   /* DS5400 MIPSfair */
0731         panic("Don't know how to set this up!");
0732         break;
0733     case MACH_DS5500:   /* DS5500 MIPSfair-2 */
0734         panic("Don't know how to set this up!");
0735         break;
0736     }
0737 
0738     /* Free the FPU interrupt if the exception is present. */
0739     if (!cpu_has_nofpuex) {
0740         cpu_fpu_mask = 0;
0741         dec_interrupt[DEC_IRQ_FPU] = -1;
0742     }
0743     /* Free the halt interrupt unused on R4k systems.  */
0744     if (current_cpu_type() == CPU_R4000SC ||
0745         current_cpu_type() == CPU_R4400SC)
0746         dec_interrupt[DEC_IRQ_HALT] = -1;
0747 
0748     /* Register board interrupts: FPU and cascade. */
0749     if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) &&
0750         dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
0751         struct irq_desc *desc_fpu;
0752         int irq_fpu;
0753 
0754         irq_fpu = dec_interrupt[DEC_IRQ_FPU];
0755         if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu",
0756                 NULL))
0757             pr_err("Failed to register fpu interrupt\n");
0758         desc_fpu = irq_to_desc(irq_fpu);
0759         fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
0760     }
0761     if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) {
0762         if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action,
0763                 IRQF_NO_THREAD, "cascade", NULL))
0764             pr_err("Failed to register cascade interrupt\n");
0765     }
0766     /* Register the bus error interrupt. */
0767     if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) {
0768         if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler,
0769                 busirq_flags, "bus error", busirq_handler))
0770             pr_err("Failed to register bus error interrupt\n");
0771     }
0772     /* Register the HALT interrupt. */
0773     if (dec_interrupt[DEC_IRQ_HALT] >= 0) {
0774         if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt,
0775                 IRQF_NO_THREAD, "halt", NULL))
0776             pr_err("Failed to register halt interrupt\n");
0777     }
0778 }
0779 
0780 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
0781 {
0782     do_IRQ(irq);
0783     return 0;
0784 }
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