mips/dec/kn02xa-berr.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Bus error event handling code for 5000-series systems equipped
0004  *  with parity error detection logic, i.e. DECstation/DECsystem
0005  *  5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
0006  *  DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
0007  *  (KN04-CA) systems.
0008  *
0009  *  Copyright (c) 2005  Maciej W. Rozycki
0010  */
0011
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/types.h>
0016
0017 #include <asm/addrspace.h>
0018 #include <asm/cpu-type.h>
0019 #include <asm/irq_regs.h>
0020 #include <asm/ptrace.h>
0021 #include <asm/traps.h>
0022
0023 #include <asm/dec/kn02ca.h>
0024 #include <asm/dec/kn02xa.h>
0025 #include <asm/dec/kn05.h>
0026
0027 static inline void dec_kn02xa_be_ack(void)
0028 {
0029     volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
0030     volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
0031
0032     *mer = KN02CA_MER_INTR;     /* Clear errors; keep the ARC IRQ. */
0033     *mem_intr = 0;          /* Any write clears the bus IRQ. */
0034     iob();
0035 }
0036
0037 static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
0038                  int invoker)
0039 {
0040     volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
0041     volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
0042
0043     static const char excstr[] = "exception";
0044     static const char intstr[] = "interrupt";
0045     static const char cpustr[] = "CPU";
0046     static const char mreadstr[] = "memory read";
0047     static const char readstr[] = "read";
0048     static const char writestr[] = "write";
0049     static const char timestr[] = "timeout";
0050     static const char paritystr[] = "parity error";
0051     static const char lanestat[][4] = { " OK", "BAD" };
0052
0053     const char *kind, *agent, *cycle, *event;
0054     unsigned long address;
0055
0056     u32 mer = *kn02xa_mer;
0057     u32 ear = *kn02xa_ear;
0058     int action = MIPS_BE_FATAL;
0059
0060     /* Ack ASAP, so that any subsequent errors get caught. */
0061     dec_kn02xa_be_ack();
0062
0063     kind = invoker ? intstr : excstr;
0064
0065     /* No DMA errors? */
0066     agent = cpustr;
0067
0068     address = ear & KN02XA_EAR_ADDRESS;
0069
0070     /* Low 256MB is decoded as memory, high -- as TC. */
0071     if (address < 0x10000000) {
0072         cycle = mreadstr;
0073         event = paritystr;
0074     } else {
0075         cycle = invoker ? writestr : readstr;
0076         event = timestr;
0077     }
0078
0079     if (is_fixup)
0080         action = MIPS_BE_FIXUP;
0081
0082     if (action != MIPS_BE_FIXUP)
0083         printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
0084             kind, agent, cycle, event, address);
0085
0086     if (action != MIPS_BE_FIXUP && address < 0x10000000)
0087         printk(KERN_ALERT "  Byte lane status %#3x -- "
0088                "#3: %s, #2: %s, #1: %s, #0: %s\n",
0089                (mer & KN02XA_MER_BYTERR) >> 8,
0090                lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
0091                lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
0092                lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
0093                lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
0094
0095     return action;
0096 }
0097
0098 int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
0099 {
0100     return dec_kn02xa_be_backend(regs, is_fixup, 0);
0101 }
0102
0103 irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id)
0104 {
0105     struct pt_regs *regs = get_irq_regs();
0106     int action = dec_kn02xa_be_backend(regs, 0, 1);
0107
0108     if (action == MIPS_BE_DISCARD)
0109         return IRQ_HANDLED;
0110
0111     /*
0112      * FIXME: Find the affected processes and kill them, otherwise
0113      * we must die.
0114      *
0115      * The interrupt is asynchronously delivered thus EPC and RA
0116      * may be irrelevant, but are printed for a reference.
0117      */
0118     printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
0119            regs->cp0_epc, regs->regs[31]);
0120     die("Unrecoverable bus error", regs);
0121 }
0122
0123
0124 void __init dec_kn02xa_be_init(void)
0125 {
0126     volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
0127
0128     /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
0129     if (current_cpu_type() == CPU_R4000SC)
0130         *mbcs |= KN4K_MB_CSR_EE;
0131     fast_iob();
0132
0133     /* Clear any leftover errors from the firmware. */
0134     dec_kn02xa_be_ack();
0135 }