mips/dec/kn01-berr.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Bus error event handling code for DECstation/DECsystem 3100
0004  *  and 2100 (KN01) systems equipped with parity error detection
0005  *  logic.
0006  *
0007  *  Copyright (c) 2005  Maciej W. Rozycki
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/kernel.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/types.h>
0015
0016 #include <asm/inst.h>
0017 #include <asm/irq_regs.h>
0018 #include <asm/mipsregs.h>
0019 #include <asm/page.h>
0020 #include <asm/ptrace.h>
0021 #include <asm/traps.h>
0022 #include <linux/uaccess.h>
0023
0024 #include <asm/dec/kn01.h>
0025
0026
0027 /* CP0 hazard avoidance. */
0028 #define BARRIER             \
0029     __asm__ __volatile__(       \
0030         ".set   push\n\t"   \
0031         ".set   noreorder\n\t"  \
0032         "nop\n\t"       \
0033         ".set   pop\n\t")
0034
0035 /*
0036  * Bits 7:0 of the Control Register are write-only -- the
0037  * corresponding bits of the Status Register have a different
0038  * meaning.  Hence we use a cache.  It speeds up things a bit
0039  * as well.
0040  *
0041  * There is no default value -- it has to be initialized.
0042  */
0043 u16 cached_kn01_csr;
0044 static DEFINE_RAW_SPINLOCK(kn01_lock);
0045
0046
0047 static inline void dec_kn01_be_ack(void)
0048 {
0049     volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
0050     unsigned long flags;
0051
0052     raw_spin_lock_irqsave(&kn01_lock, flags);
0053
0054     *csr = cached_kn01_csr | KN01_CSR_MEMERR;   /* Clear bus IRQ. */
0055     iob();
0056
0057     raw_spin_unlock_irqrestore(&kn01_lock, flags);
0058 }
0059
0060 static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
0061 {
0062     volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
0063                             KN01_ERRADDR);
0064
0065     static const char excstr[] = "exception";
0066     static const char intstr[] = "interrupt";
0067     static const char cpustr[] = "CPU";
0068     static const char mreadstr[] = "memory read";
0069     static const char readstr[] = "read";
0070     static const char writestr[] = "write";
0071     static const char timestr[] = "timeout";
0072     static const char paritystr[] = "parity error";
0073
0074     int data = regs->cp0_cause & 4;
0075     unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
0076                   ((regs->cp0_cause & CAUSEF_BD) != 0);
0077     union mips_instruction insn;
0078     unsigned long entrylo, offset;
0079     long asid, entryhi, vaddr;
0080
0081     const char *kind, *agent, *cycle, *event;
0082     unsigned long address;
0083
0084     u32 erraddr = *kn01_erraddr;
0085     int action = MIPS_BE_FATAL;
0086
0087     /* Ack ASAP, so that any subsequent errors get caught. */
0088     dec_kn01_be_ack();
0089
0090     kind = invoker ? intstr : excstr;
0091
0092     agent = cpustr;
0093
0094     if (invoker)
0095         address = erraddr;
0096     else {
0097         /* Bloody hardware doesn't record the address for reads... */
0098         if (data) {
0099             /* This never faults. */
0100             __get_user(insn.word, pc);
0101             vaddr = regs->regs[insn.i_format.rs] +
0102                 insn.i_format.simmediate;
0103         } else
0104             vaddr = (long)pc;
0105         if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
0106             address = CPHYSADDR(vaddr);
0107         else {
0108             /* Peek at what physical address the CPU used. */
0109             asid = read_c0_entryhi();
0110             entryhi = asid & (PAGE_SIZE - 1);
0111             entryhi |= vaddr & ~(PAGE_SIZE - 1);
0112             write_c0_entryhi(entryhi);
0113             BARRIER;
0114             tlb_probe();
0115             /* No need to check for presence. */
0116             tlb_read();
0117             entrylo = read_c0_entrylo0();
0118             write_c0_entryhi(asid);
0119             offset = vaddr & (PAGE_SIZE - 1);
0120             address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
0121         }
0122     }
0123
0124     /* Treat low 256MB as memory, high -- as I/O. */
0125     if (address < 0x10000000) {
0126         cycle = mreadstr;
0127         event = paritystr;
0128     } else {
0129         cycle = invoker ? writestr : readstr;
0130         event = timestr;
0131     }
0132
0133     if (is_fixup)
0134         action = MIPS_BE_FIXUP;
0135
0136     if (action != MIPS_BE_FIXUP)
0137         printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
0138             kind, agent, cycle, event, address);
0139
0140     return action;
0141 }
0142
0143 int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
0144 {
0145     return dec_kn01_be_backend(regs, is_fixup, 0);
0146 }
0147
0148 irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id)
0149 {
0150     volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
0151     struct pt_regs *regs = get_irq_regs();
0152     int action;
0153
0154     if (!(*csr & KN01_CSR_MEMERR))
0155         return IRQ_NONE;        /* Must have been video. */
0156
0157     action = dec_kn01_be_backend(regs, 0, 1);
0158
0159     if (action == MIPS_BE_DISCARD)
0160         return IRQ_HANDLED;
0161
0162     /*
0163      * FIXME: Find the affected processes and kill them, otherwise
0164      * we must die.
0165      *
0166      * The interrupt is asynchronously delivered thus EPC and RA
0167      * may be irrelevant, but are printed for a reference.
0168      */
0169     printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
0170            regs->cp0_epc, regs->regs[31]);
0171     die("Unrecoverable bus error", regs);
0172 }
0173
0174
0175 void __init dec_kn01_be_init(void)
0176 {
0177     volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
0178     unsigned long flags;
0179
0180     raw_spin_lock_irqsave(&kn01_lock, flags);
0181
0182     /* Preset write-only bits of the Control Register cache. */
0183     cached_kn01_csr = *csr;
0184     cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
0185     cached_kn01_csr |= KN01_CSR_LEDS;
0186
0187     /* Enable parity error detection. */
0188     cached_kn01_csr &= ~KN01_CSR_PARDIS;
0189     *csr = cached_kn01_csr;
0190     iob();
0191
0192     raw_spin_unlock_irqrestore(&kn01_lock, flags);
0193
0194     /* Clear any leftover errors from the firmware. */
0195     dec_kn01_be_ack();
0196 }