mips/dec/ioasic-irq.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  DEC I/O ASIC interrupts.
0004  *
0005  *  Copyright (c) 2002, 2003, 2013  Maciej W. Rozycki
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/irq.h>
0010 #include <linux/types.h>
0011
0012 #include <asm/dec/ioasic.h>
0013 #include <asm/dec/ioasic_addrs.h>
0014 #include <asm/dec/ioasic_ints.h>
0015
0016 static int ioasic_irq_base;
0017
0018 static void unmask_ioasic_irq(struct irq_data *d)
0019 {
0020     u32 simr;
0021
0022     simr = ioasic_read(IO_REG_SIMR);
0023     simr |= (1 << (d->irq - ioasic_irq_base));
0024     ioasic_write(IO_REG_SIMR, simr);
0025 }
0026
0027 static void mask_ioasic_irq(struct irq_data *d)
0028 {
0029     u32 simr;
0030
0031     simr = ioasic_read(IO_REG_SIMR);
0032     simr &= ~(1 << (d->irq - ioasic_irq_base));
0033     ioasic_write(IO_REG_SIMR, simr);
0034 }
0035
0036 static void ack_ioasic_irq(struct irq_data *d)
0037 {
0038     mask_ioasic_irq(d);
0039     fast_iob();
0040 }
0041
0042 static struct irq_chip ioasic_irq_type = {
0043     .name = "IO-ASIC",
0044     .irq_ack = ack_ioasic_irq,
0045     .irq_mask = mask_ioasic_irq,
0046     .irq_mask_ack = ack_ioasic_irq,
0047     .irq_unmask = unmask_ioasic_irq,
0048 };
0049
0050 static void clear_ioasic_dma_irq(struct irq_data *d)
0051 {
0052     u32 sir;
0053
0054     sir = ~(1 << (d->irq - ioasic_irq_base));
0055     ioasic_write(IO_REG_SIR, sir);
0056     fast_iob();
0057 }
0058
0059 static struct irq_chip ioasic_dma_irq_type = {
0060     .name = "IO-ASIC-DMA",
0061     .irq_ack = clear_ioasic_dma_irq,
0062     .irq_mask = mask_ioasic_irq,
0063     .irq_unmask = unmask_ioasic_irq,
0064     .irq_eoi = clear_ioasic_dma_irq,
0065 };
0066
0067 /*
0068  * I/O ASIC implements two kinds of DMA interrupts, informational and
0069  * error interrupts.
0070  *
0071  * The former do not stop DMA and should be cleared as soon as possible
0072  * so that if they retrigger before the handler has completed, usually as
0073  * a side effect of actions taken by the handler, then they are reissued.
0074  * These use the `handle_edge_irq' handler that clears the request right
0075  * away.
0076  *
0077  * The latter stop DMA and do not resume it until the interrupt has been
0078  * cleared.  This cannot be done until after a corrective action has been
0079  * taken and this also means they will not retrigger.  Therefore they use
0080  * the `handle_fasteoi_irq' handler that only clears the request on the
0081  * way out.  Because MIPS processor interrupt inputs, one of which the I/O
0082  * ASIC is cascaded to, are level-triggered it is recommended that error
0083  * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
0084  * set so that they are run with the interrupt line masked.
0085  *
0086  * This mask has `1' bits in the positions of informational interrupts.
0087  */
0088 #define IO_IRQ_DMA_INFO                         \
0089     (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) |              \
0090      IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) |              \
0091      IO_IRQ_MASK(IO_INR_ISDN_TXDMA) |               \
0092      IO_IRQ_MASK(IO_INR_ISDN_RXDMA) |               \
0093      IO_IRQ_MASK(IO_INR_ASC_DMA))
0094
0095 void __init init_ioasic_irqs(int base)
0096 {
0097     int i;
0098
0099     /* Mask interrupts. */
0100     ioasic_write(IO_REG_SIMR, 0);
0101     fast_iob();
0102
0103     for (i = base; i < base + IO_INR_DMA; i++)
0104         irq_set_chip_and_handler(i, &ioasic_irq_type,
0105                      handle_level_irq);
0106     for (; i < base + IO_IRQ_LINES; i++)
0107         irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
0108                      1 << (i - base) & IO_IRQ_DMA_INFO ?
0109                      handle_edge_irq : handle_fasteoi_irq);
0110
0111     ioasic_irq_base = base;
0112 }