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0001 /*
0002  * XHCI HCD glue for Cavium Octeon III SOCs.
0003  *
0004  * Copyright (C) 2010-2017 Cavium Networks
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file "COPYING" in the main directory of this archive
0008  * for more details.
0009  */
0010 
0011 #include <linux/module.h>
0012 #include <linux/device.h>
0013 #include <linux/mutex.h>
0014 #include <linux/delay.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/io.h>
0017 
0018 #include <asm/octeon/octeon.h>
0019 
0020 /* USB Control Register */
0021 union cvm_usbdrd_uctl_ctl {
0022     uint64_t u64;
0023     struct cvm_usbdrd_uctl_ctl_s {
0024     /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
0025     __BITFIELD_FIELD(uint64_t clear_bist:1,
0026     /* 1 = Start BIST and cleared by hardware */
0027     __BITFIELD_FIELD(uint64_t start_bist:1,
0028     /* Reference clock select for SuperSpeed and HighSpeed PLLs:
0029      *  0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
0030      *  0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
0031      *  0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
0032      *        HighSpeed PLL uses PLL_REF_CLK for reference clck
0033      *  0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
0034      *        HighSpeed PLL uses PLL_REF_CLK for reference clck
0035      */
0036     __BITFIELD_FIELD(uint64_t ref_clk_sel:2,
0037     /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
0038     __BITFIELD_FIELD(uint64_t ssc_en:1,
0039     /* Spread-spectrum clock modulation range:
0040      *  0x0 = -4980 ppm downspread
0041      *  0x1 = -4492 ppm downspread
0042      *  0x2 = -4003 ppm downspread
0043      *  0x3 - 0x7 = Reserved
0044      */
0045     __BITFIELD_FIELD(uint64_t ssc_range:3,
0046     /* Enable non-standard oscillator frequencies:
0047      *  [55:53] = modules -1
0048      *  [52:47] = 2's complement push amount, 0 = Feature disabled
0049      */
0050     __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
0051     /* Reference clock multiplier for non-standard frequencies:
0052      *  0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
0053      *  0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
0054      *  0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
0055      *  Other Values = Reserved
0056      */
0057     __BITFIELD_FIELD(uint64_t mpll_multiplier:7,
0058     /* Enable reference clock to prescaler for SuperSpeed functionality.
0059      * Should always be set to "1"
0060      */
0061     __BITFIELD_FIELD(uint64_t ref_ssp_en:1,
0062     /* Divide the reference clock by 2 before entering the
0063      * REF_CLK_FSEL divider:
0064      *  If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
0065      *  If REF_CLK_SEL = 0x2 or 0x3, then:
0066      *      0x1 = DLMC_REF_CLK* is 125MHz
0067      *      0x0 = DLMC_REF_CLK* is another supported frequency
0068      */
0069     __BITFIELD_FIELD(uint64_t ref_clk_div2:1,
0070     /* Select reference clock freqnuency for both PLL blocks:
0071      *  0x27 = REF_CLK_SEL is 0x0 or 0x1
0072      *  0x07 = REF_CLK_SEL is 0x2 or 0x3
0073      */
0074     __BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
0075     /* Reserved */
0076     __BITFIELD_FIELD(uint64_t reserved_31_31:1,
0077     /* Controller clock enable. */
0078     __BITFIELD_FIELD(uint64_t h_clk_en:1,
0079     /* Select bypass input to controller clock divider:
0080      *  0x0 = Use divided coprocessor clock from H_CLKDIV
0081      *  0x1 = Use clock from GPIO pins
0082      */
0083     __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
0084     /* Reset controller clock divider. */
0085     __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
0086     /* Reserved */
0087     __BITFIELD_FIELD(uint64_t reserved_27_27:1,
0088     /* Clock divider select:
0089      *  0x0 = divide by 1
0090      *  0x1 = divide by 2
0091      *  0x2 = divide by 4
0092      *  0x3 = divide by 6
0093      *  0x4 = divide by 8
0094      *  0x5 = divide by 16
0095      *  0x6 = divide by 24
0096      *  0x7 = divide by 32
0097      */
0098     __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
0099     /* Reserved */
0100     __BITFIELD_FIELD(uint64_t reserved_22_23:2,
0101     /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
0102     __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
0103     /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
0104     __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
0105     /* Reserved */
0106     __BITFIELD_FIELD(uint64_t reserved_19_19:1,
0107     /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
0108     __BITFIELD_FIELD(uint64_t usb3_port_disable:1,
0109     /* Reserved */
0110     __BITFIELD_FIELD(uint64_t reserved_17_17:1,
0111     /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
0112     __BITFIELD_FIELD(uint64_t usb2_port_disable:1,
0113     /* Reserved */
0114     __BITFIELD_FIELD(uint64_t reserved_15_15:1,
0115     /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
0116     __BITFIELD_FIELD(uint64_t ss_power_en:1,
0117     /* Reserved */
0118     __BITFIELD_FIELD(uint64_t reserved_13_13:1,
0119     /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
0120     __BITFIELD_FIELD(uint64_t hs_power_en:1,
0121     /* Reserved */
0122     __BITFIELD_FIELD(uint64_t reserved_5_11:7,
0123     /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
0124     __BITFIELD_FIELD(uint64_t csclk_en:1,
0125     /* Controller mode: 0x0 = Host, 0x1 = Device */
0126     __BITFIELD_FIELD(uint64_t drd_mode:1,
0127     /* PHY reset */
0128     __BITFIELD_FIELD(uint64_t uphy_rst:1,
0129     /* Software reset UAHC */
0130     __BITFIELD_FIELD(uint64_t uahc_rst:1,
0131     /* Software resets UCTL */
0132     __BITFIELD_FIELD(uint64_t uctl_rst:1,
0133     ;)))))))))))))))))))))))))))))))))
0134     } s;
0135 };
0136 
0137 /* UAHC Configuration Register */
0138 union cvm_usbdrd_uctl_host_cfg {
0139     uint64_t u64;
0140     struct cvm_usbdrd_uctl_host_cfg_s {
0141     /* Reserved */
0142     __BITFIELD_FIELD(uint64_t reserved_60_63:4,
0143     /* Indicates minimum value of all received BELT values */
0144     __BITFIELD_FIELD(uint64_t host_current_belt:12,
0145     /* Reserved */
0146     __BITFIELD_FIELD(uint64_t reserved_38_47:10,
0147     /* HS jitter adjustment */
0148     __BITFIELD_FIELD(uint64_t fla:6,
0149     /* Reserved */
0150     __BITFIELD_FIELD(uint64_t reserved_29_31:3,
0151     /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
0152     __BITFIELD_FIELD(uint64_t bme:1,
0153     /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
0154     __BITFIELD_FIELD(uint64_t oci_en:1,
0155     /* Overcurrent sene selection:
0156      *  0x0 = Overcurrent indication from off-chip is active-low
0157      *  0x1 = Overcurrent indication from off-chip is active-high
0158      */
0159     __BITFIELD_FIELD(uint64_t oci_active_high_en:1,
0160     /* Port power control enable: 0x0 = unavailable, 0x1 = available */
0161     __BITFIELD_FIELD(uint64_t ppc_en:1,
0162     /* Port power control sense selection:
0163      *  0x0 = Port power to off-chip is active-low
0164      *  0x1 = Port power to off-chip is active-high
0165      */
0166     __BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
0167     /* Reserved */
0168     __BITFIELD_FIELD(uint64_t reserved_0_23:24,
0169     ;)))))))))))
0170     } s;
0171 };
0172 
0173 /* UCTL Shim Features Register */
0174 union cvm_usbdrd_uctl_shim_cfg {
0175     uint64_t u64;
0176     struct cvm_usbdrd_uctl_shim_cfg_s {
0177     /* Out-of-bound UAHC register access: 0 = read, 1 = write */
0178     __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
0179     /* Reserved */
0180     __BITFIELD_FIELD(uint64_t reserved_60_62:3,
0181     /* SRCID error log for out-of-bound UAHC register access:
0182      *  [59:58] = chipID
0183      *  [57] = Request source: 0 = core, 1 = NCB-device
0184      *  [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
0185      *  [50:48] = SubID
0186      */
0187     __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
0188     /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
0189     __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
0190     /* Reserved */
0191     __BITFIELD_FIELD(uint64_t reserved_44_46:3,
0192     /* Encoded error type for bad UAHC DMA */
0193     __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
0194     /* Reserved */
0195     __BITFIELD_FIELD(uint64_t reserved_13_39:27,
0196     /* Select the IOI read command used by DMA accesses */
0197     __BITFIELD_FIELD(uint64_t dma_read_cmd:1,
0198     /* Reserved */
0199     __BITFIELD_FIELD(uint64_t reserved_10_11:2,
0200     /* Select endian format for DMA accesses to the L2c:
0201      *  0x0 = Little endian
0202      *` 0x1 = Big endian
0203      *  0x2 = Reserved
0204      *  0x3 = Reserved
0205      */
0206     __BITFIELD_FIELD(uint64_t dma_endian_mode:2,
0207     /* Reserved */
0208     __BITFIELD_FIELD(uint64_t reserved_2_7:6,
0209     /* Select endian format for IOI CSR access to UAHC:
0210      *  0x0 = Little endian
0211      *` 0x1 = Big endian
0212      *  0x2 = Reserved
0213      *  0x3 = Reserved
0214      */
0215     __BITFIELD_FIELD(uint64_t csr_endian_mode:2,
0216     ;))))))))))))
0217     } s;
0218 };
0219 
0220 #define OCTEON_H_CLKDIV_SEL     8
0221 #define OCTEON_MIN_H_CLK_RATE       150000000
0222 #define OCTEON_MAX_H_CLK_RATE       300000000
0223 
0224 static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
0225 static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
0226 
0227 
0228 static int dwc3_octeon_config_power(struct device *dev, u64 base)
0229 {
0230 #define UCTL_HOST_CFG   0xe0
0231     union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
0232     union cvmx_gpio_bit_cfgx gpio_bit;
0233     uint32_t gpio_pwr[3];
0234     int gpio, len, power_active_low;
0235     struct device_node *node = dev->of_node;
0236     int index = (base >> 24) & 1;
0237 
0238     if (of_find_property(node, "power", &len) != NULL) {
0239         if (len == 12) {
0240             of_property_read_u32_array(node, "power", gpio_pwr, 3);
0241             power_active_low = gpio_pwr[2] & 0x01;
0242             gpio = gpio_pwr[1];
0243         } else if (len == 8) {
0244             of_property_read_u32_array(node, "power", gpio_pwr, 2);
0245             power_active_low = 0;
0246             gpio = gpio_pwr[1];
0247         } else {
0248             dev_err(dev, "dwc3 controller clock init failure.\n");
0249             return -EINVAL;
0250         }
0251         if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
0252             OCTEON_IS_MODEL(OCTEON_CNF75XX))
0253             && gpio <= 31) {
0254             gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
0255             gpio_bit.s.tx_oe = 1;
0256             gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
0257             cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
0258         } else if (gpio <= 15) {
0259             gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
0260             gpio_bit.s.tx_oe = 1;
0261             gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
0262             cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
0263         } else {
0264             gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
0265             gpio_bit.s.tx_oe = 1;
0266             gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
0267             cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
0268         }
0269 
0270         /* Enable XHCI power control and set if active high or low. */
0271         uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
0272         uctl_host_cfg.s.ppc_en = 1;
0273         uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
0274         cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
0275     } else {
0276         /* Disable XHCI power control and set if active high. */
0277         uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
0278         uctl_host_cfg.s.ppc_en = 0;
0279         uctl_host_cfg.s.ppc_active_high_en = 0;
0280         cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
0281         dev_warn(dev, "dwc3 controller clock init failure.\n");
0282     }
0283     return 0;
0284 }
0285 
0286 static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
0287 {
0288     union cvm_usbdrd_uctl_ctl uctl_ctl;
0289     int ref_clk_sel = 2;
0290     u64 div;
0291     u32 clock_rate;
0292     int mpll_mul;
0293     int i;
0294     u64 h_clk_rate;
0295     u64 uctl_ctl_reg = base;
0296 
0297     if (dev->of_node) {
0298         const char *ss_clock_type;
0299         const char *hs_clock_type;
0300 
0301         i = of_property_read_u32(dev->of_node,
0302                      "refclk-frequency", &clock_rate);
0303         if (i) {
0304             pr_err("No UCTL \"refclk-frequency\"\n");
0305             return -EINVAL;
0306         }
0307         i = of_property_read_string(dev->of_node,
0308                         "refclk-type-ss", &ss_clock_type);
0309         if (i) {
0310             pr_err("No UCTL \"refclk-type-ss\"\n");
0311             return -EINVAL;
0312         }
0313         i = of_property_read_string(dev->of_node,
0314                         "refclk-type-hs", &hs_clock_type);
0315         if (i) {
0316             pr_err("No UCTL \"refclk-type-hs\"\n");
0317             return -EINVAL;
0318         }
0319         if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
0320             if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
0321                 ref_clk_sel = 0;
0322             else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
0323                 ref_clk_sel = 2;
0324             else
0325                 pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",
0326                        hs_clock_type);
0327         } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
0328             if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
0329                 ref_clk_sel = 1;
0330             else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
0331                 ref_clk_sel = 3;
0332             else {
0333                 pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",
0334                        hs_clock_type);
0335                 ref_clk_sel = 3;
0336             }
0337         } else
0338             pr_err("Invalid SS clock type %s, using  dlmc_ref_clk0 instead\n",
0339                    ss_clock_type);
0340 
0341         if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
0342                   (clock_rate != 100000000))
0343             pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
0344                    clock_rate);
0345 
0346     } else {
0347         pr_err("No USB UCTL device node\n");
0348         return -EINVAL;
0349     }
0350 
0351     /*
0352      * Step 1: Wait for all voltages to be stable...that surely
0353      *         happened before starting the kernel. SKIP
0354      */
0355 
0356     /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
0357 
0358     /* Step 3: Assert all resets. */
0359     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0360     uctl_ctl.s.uphy_rst = 1;
0361     uctl_ctl.s.uahc_rst = 1;
0362     uctl_ctl.s.uctl_rst = 1;
0363     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0364 
0365     /* Step 4a: Reset the clock dividers. */
0366     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0367     uctl_ctl.s.h_clkdiv_rst = 1;
0368     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0369 
0370     /* Step 4b: Select controller clock frequency. */
0371     for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
0372         h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
0373         if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
0374                  h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
0375             break;
0376     }
0377     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0378     uctl_ctl.s.h_clkdiv_sel = div;
0379     uctl_ctl.s.h_clk_en = 1;
0380     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0381     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0382     if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
0383         dev_err(dev, "dwc3 controller clock init failure.\n");
0384             return -EINVAL;
0385     }
0386 
0387     /* Step 4c: Deassert the controller clock divider reset. */
0388     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0389     uctl_ctl.s.h_clkdiv_rst = 0;
0390     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0391 
0392     /* Step 5a: Reference clock configuration. */
0393     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0394     uctl_ctl.s.ref_clk_sel = ref_clk_sel;
0395     uctl_ctl.s.ref_clk_fsel = 0x07;
0396     uctl_ctl.s.ref_clk_div2 = 0;
0397     switch (clock_rate) {
0398     default:
0399         dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
0400             clock_rate);
0401         fallthrough;
0402     case 100000000:
0403         mpll_mul = 0x19;
0404         if (ref_clk_sel < 2)
0405             uctl_ctl.s.ref_clk_fsel = 0x27;
0406         break;
0407     case 50000000:
0408         mpll_mul = 0x32;
0409         break;
0410     case 125000000:
0411         mpll_mul = 0x28;
0412         break;
0413     }
0414     uctl_ctl.s.mpll_multiplier = mpll_mul;
0415 
0416     /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
0417     uctl_ctl.s.ssc_en = 1;
0418 
0419     /* Step 5c: Enable SuperSpeed. */
0420     uctl_ctl.s.ref_ssp_en = 1;
0421 
0422     /* Step 5d: Configure PHYs. SKIP */
0423 
0424     /* Step 6a & 6b: Power up PHYs. */
0425     uctl_ctl.s.hs_power_en = 1;
0426     uctl_ctl.s.ss_power_en = 1;
0427     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0428 
0429     /* Step 7: Wait 10 controller-clock cycles to take effect. */
0430     udelay(10);
0431 
0432     /* Step 8a: Deassert UCTL reset signal. */
0433     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0434     uctl_ctl.s.uctl_rst = 0;
0435     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0436 
0437     /* Step 8b: Wait 10 controller-clock cycles. */
0438     udelay(10);
0439 
0440     /* Steo 8c: Setup power-power control. */
0441     if (dwc3_octeon_config_power(dev, base)) {
0442         dev_err(dev, "Error configuring power.\n");
0443         return -EINVAL;
0444     }
0445 
0446     /* Step 8d: Deassert UAHC reset signal. */
0447     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0448     uctl_ctl.s.uahc_rst = 0;
0449     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0450 
0451     /* Step 8e: Wait 10 controller-clock cycles. */
0452     udelay(10);
0453 
0454     /* Step 9: Enable conditional coprocessor clock of UCTL. */
0455     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0456     uctl_ctl.s.csclk_en = 1;
0457     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0458 
0459     /*Step 10: Set for host mode only. */
0460     uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
0461     uctl_ctl.s.drd_mode = 0;
0462     cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
0463 
0464     return 0;
0465 }
0466 
0467 static void __init dwc3_octeon_set_endian_mode(u64 base)
0468 {
0469 #define UCTL_SHIM_CFG   0xe8
0470     union cvm_usbdrd_uctl_shim_cfg shim_cfg;
0471 
0472     shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
0473 #ifdef __BIG_ENDIAN
0474     shim_cfg.s.dma_endian_mode = 1;
0475     shim_cfg.s.csr_endian_mode = 1;
0476 #else
0477     shim_cfg.s.dma_endian_mode = 0;
0478     shim_cfg.s.csr_endian_mode = 0;
0479 #endif
0480     cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
0481 }
0482 
0483 #define CVMX_USBDRDX_UCTL_CTL(index)                \
0484         (CVMX_ADD_IO_SEG(0x0001180068000000ull) +   \
0485         ((index & 1) * 0x1000000ull))
0486 static void __init dwc3_octeon_phy_reset(u64 base)
0487 {
0488     union cvm_usbdrd_uctl_ctl uctl_ctl;
0489     int index = (base >> 24) & 1;
0490 
0491     uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
0492     uctl_ctl.s.uphy_rst = 0;
0493     cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
0494 }
0495 
0496 static int __init dwc3_octeon_device_init(void)
0497 {
0498     const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
0499     struct platform_device *pdev;
0500     struct device_node *node;
0501     struct resource *res;
0502     void __iomem *base;
0503 
0504     /*
0505      * There should only be three universal controllers, "uctl"
0506      * in the device tree. Two USB and a SATA, which we ignore.
0507      */
0508     node = NULL;
0509     do {
0510         node = of_find_node_by_name(node, "uctl");
0511         if (!node)
0512             return -ENODEV;
0513 
0514         if (of_device_is_compatible(node, compat_node_name)) {
0515             pdev = of_find_device_by_node(node);
0516             if (!pdev)
0517                 return -ENODEV;
0518 
0519             /*
0520              * The code below maps in the registers necessary for
0521              * setting up the clocks and reseting PHYs. We must
0522              * release the resources so the dwc3 subsystem doesn't
0523              * know the difference.
0524              */
0525             base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0526             if (IS_ERR(base)) {
0527                 put_device(&pdev->dev);
0528                 return PTR_ERR(base);
0529             }
0530 
0531             mutex_lock(&dwc3_octeon_clocks_mutex);
0532             dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
0533             dwc3_octeon_set_endian_mode((u64)base);
0534             dwc3_octeon_phy_reset((u64)base);
0535             dev_info(&pdev->dev, "clocks initialized.\n");
0536             mutex_unlock(&dwc3_octeon_clocks_mutex);
0537             devm_iounmap(&pdev->dev, base);
0538             devm_release_mem_region(&pdev->dev, res->start,
0539                         resource_size(res));
0540             put_device(&pdev->dev);
0541         }
0542     } while (node != NULL);
0543 
0544     return 0;
0545 }
0546 device_initcall(dwc3_octeon_device_init);
0547 
0548 MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
0549 MODULE_LICENSE("GPL");
0550 MODULE_DESCRIPTION("USB driver for OCTEON III SoC");
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