mips/cavium-octeon/oct_ilm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/fs.h>
0003 #include <linux/interrupt.h>
0004 #include <asm/octeon/octeon.h>
0005 #include <asm/octeon/cvmx-ciu-defs.h>
0006 #include <asm/octeon/cvmx.h>
0007 #include <linux/debugfs.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/seq_file.h>
0011
0012 #define TIMER_NUM 3
0013
0014 static bool reset_stats;
0015
0016 struct latency_info {
0017     u64 io_interval;
0018     u64 cpu_interval;
0019     u64 timer_start1;
0020     u64 timer_start2;
0021     u64 max_latency;
0022     u64 min_latency;
0023     u64 latency_sum;
0024     u64 average_latency;
0025     u64 interrupt_cnt;
0026 };
0027
0028 static struct latency_info li;
0029 static struct dentry *dir;
0030
0031 static int show_latency(struct seq_file *m, void *v)
0032 {
0033     u64 cpuclk, avg, max, min;
0034     struct latency_info curr_li = li;
0035
0036     cpuclk = octeon_get_clock_rate();
0037
0038     max = (curr_li.max_latency * 1000000000) / cpuclk;
0039     min = (curr_li.min_latency * 1000000000) / cpuclk;
0040     avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt);
0041
0042     seq_printf(m, "cnt: %10lld, avg: %7lld ns, max: %7lld ns, min: %7lld ns\n",
0043            curr_li.interrupt_cnt, avg, max, min);
0044     return 0;
0045 }
0046
0047 static int oct_ilm_open(struct inode *inode, struct file *file)
0048 {
0049     return single_open(file, show_latency, NULL);
0050 }
0051
0052 static const struct file_operations oct_ilm_ops = {
0053     .open = oct_ilm_open,
0054     .read = seq_read,
0055     .llseek = seq_lseek,
0056     .release = single_release,
0057 };
0058
0059 static int reset_statistics(void *data, u64 value)
0060 {
0061     reset_stats = true;
0062     return 0;
0063 }
0064
0065 DEFINE_DEBUGFS_ATTRIBUTE(reset_statistics_ops, NULL, reset_statistics, "%llu\n");
0066
0067 static void init_debugfs(void)
0068 {
0069     dir = debugfs_create_dir("oct_ilm", 0);
0070     debugfs_create_file("statistics", 0222, dir, NULL, &oct_ilm_ops);
0071     debugfs_create_file("reset", 0222, dir, NULL, &reset_statistics_ops);
0072 }
0073
0074 static void init_latency_info(struct latency_info *li, int startup)
0075 {
0076     /* interval in milli seconds after which the interrupt will
0077      * be triggered
0078      */
0079     int interval = 1;
0080
0081     if (startup) {
0082         /* Calculating by the amounts io clock and cpu clock would
0083          *  increment in interval amount of ms
0084          */
0085         li->io_interval = (octeon_get_io_clock_rate() * interval) / 1000;
0086         li->cpu_interval = (octeon_get_clock_rate() * interval) / 1000;
0087     }
0088     li->timer_start1 = 0;
0089     li->timer_start2 = 0;
0090     li->max_latency = 0;
0091     li->min_latency = (u64)-1;
0092     li->latency_sum = 0;
0093     li->interrupt_cnt = 0;
0094 }
0095
0096
0097 static void start_timer(int timer, u64 interval)
0098 {
0099     union cvmx_ciu_timx timx;
0100     unsigned long flags;
0101
0102     timx.u64 = 0;
0103     timx.s.one_shot = 1;
0104     timx.s.len = interval;
0105     raw_local_irq_save(flags);
0106     li.timer_start1 = read_c0_cvmcount();
0107     cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
0108     /* Read it back to force wait until register is written. */
0109     timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
0110     li.timer_start2 = read_c0_cvmcount();
0111     raw_local_irq_restore(flags);
0112 }
0113
0114
0115 static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
0116 {
0117     u64 last_latency;
0118     u64 last_int_cnt;
0119
0120     if (reset_stats) {
0121         init_latency_info(&li, 0);
0122         reset_stats = false;
0123     } else {
0124         last_int_cnt = read_c0_cvmcount();
0125         last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
0126         li.interrupt_cnt++;
0127         li.latency_sum += last_latency;
0128         if (last_latency > li.max_latency)
0129             li.max_latency = last_latency;
0130         if (last_latency < li.min_latency)
0131             li.min_latency = last_latency;
0132     }
0133     start_timer(TIMER_NUM, li.io_interval);
0134     return IRQ_HANDLED;
0135 }
0136
0137 static void disable_timer(int timer)
0138 {
0139     union cvmx_ciu_timx timx;
0140
0141     timx.s.one_shot = 0;
0142     timx.s.len = 0;
0143     cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
0144     /* Read it back to force immediate write of timer register*/
0145     timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
0146 }
0147
0148 static __init int oct_ilm_module_init(void)
0149 {
0150     int rc;
0151     int irq = OCTEON_IRQ_TIMER0 + TIMER_NUM;
0152
0153     init_debugfs();
0154
0155     rc = request_irq(irq, cvm_oct_ciu_timer_interrupt, IRQF_NO_THREAD,
0156              "oct_ilm", 0);
0157     if (rc) {
0158         WARN(1, "Could not acquire IRQ %d", irq);
0159         goto err_irq;
0160     }
0161
0162     init_latency_info(&li, 1);
0163     start_timer(TIMER_NUM, li.io_interval);
0164
0165     return 0;
0166 err_irq:
0167     debugfs_remove_recursive(dir);
0168     return rc;
0169 }
0170
0171 static __exit void oct_ilm_module_exit(void)
0172 {
0173     disable_timer(TIMER_NUM);
0174     debugfs_remove_recursive(dir);
0175     free_irq(OCTEON_IRQ_TIMER0 + TIMER_NUM, 0);
0176 }
0177
0178 module_exit(oct_ilm_module_exit);
0179 module_init(oct_ilm_module_init);
0180 MODULE_AUTHOR("Venkat Subbiah, Cavium");
0181 MODULE_DESCRIPTION("Measures interrupt latency on Octeon chips.");
0182 MODULE_LICENSE("GPL");