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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2008 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 /*
0029  *
0030  * Support library for the SPI
0031  */
0032 #include <asm/octeon/octeon.h>
0033 
0034 #include <asm/octeon/cvmx-config.h>
0035 
0036 #include <asm/octeon/cvmx-pko.h>
0037 #include <asm/octeon/cvmx-spi.h>
0038 
0039 #include <asm/octeon/cvmx-spxx-defs.h>
0040 #include <asm/octeon/cvmx-stxx-defs.h>
0041 #include <asm/octeon/cvmx-srxx-defs.h>
0042 
0043 #define INVOKE_CB(function_p, args...)      \
0044     do {                    \
0045         if (function_p) {       \
0046             res = function_p(args); \
0047             if (res)        \
0048                 return res; \
0049         }               \
0050     } while (0)
0051 
0052 #if CVMX_ENABLE_DEBUG_PRINTS
0053 static const char *modes[] =
0054     { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" };
0055 #endif
0056 
0057 /* Default callbacks, can be overridden
0058  *  using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks
0059  */
0060 static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
0061     .reset_cb = cvmx_spi_reset_cb,
0062     .calendar_setup_cb = cvmx_spi_calendar_setup_cb,
0063     .clock_detect_cb = cvmx_spi_clock_detect_cb,
0064     .training_cb = cvmx_spi_training_cb,
0065     .calendar_sync_cb = cvmx_spi_calendar_sync_cb,
0066     .interface_up_cb = cvmx_spi_interface_up_cb
0067 };
0068 
0069 /*
0070  * Get current SPI4 initialization callbacks
0071  *
0072  * @callbacks:  Pointer to the callbacks structure.to fill
0073  *
0074  * Returns Pointer to cvmx_spi_callbacks_t structure.
0075  */
0076 void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks)
0077 {
0078     memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks));
0079 }
0080 
0081 /*
0082  * Set new SPI4 initialization callbacks
0083  *
0084  * @new_callbacks:  Pointer to an updated callbacks structure.
0085  */
0086 void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
0087 {
0088     memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks));
0089 }
0090 
0091 /*
0092  * Initialize and start the SPI interface.
0093  *
0094  * @interface: The identifier of the packet interface to configure and
0095  *          use as a SPI interface.
0096  * @mode:      The operating mode for the SPI interface. The interface
0097  *          can operate as a full duplex (both Tx and Rx data paths
0098  *          active) or as a halfplex (either the Tx data path is
0099  *          active or the Rx data path is active, but not both).
0100  * @timeout:   Timeout to wait for clock synchronization in seconds
0101  * @num_ports: Number of SPI ports to configure
0102  *
0103  * Returns Zero on success, negative of failure.
0104  */
0105 int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
0106                  int num_ports)
0107 {
0108     int res = -1;
0109 
0110     if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
0111         return res;
0112 
0113     /* Callback to perform SPI4 reset */
0114     INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
0115 
0116     /* Callback to perform calendar setup */
0117     INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode,
0118           num_ports);
0119 
0120     /* Callback to perform clock detection */
0121     INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
0122 
0123     /* Callback to perform SPI4 link training */
0124     INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
0125 
0126     /* Callback to perform calendar sync */
0127     INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
0128           timeout);
0129 
0130     /* Callback to handle interface coming up */
0131     INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
0132 
0133     return res;
0134 }
0135 
0136 /*
0137  * This routine restarts the SPI interface after it has lost synchronization
0138  * with its correspondent system.
0139  *
0140  * @interface: The identifier of the packet interface to configure and
0141  *          use as a SPI interface.
0142  * @mode:      The operating mode for the SPI interface. The interface
0143  *          can operate as a full duplex (both Tx and Rx data paths
0144  *          active) or as a halfplex (either the Tx data path is
0145  *          active or the Rx data path is active, but not both).
0146  * @timeout:   Timeout to wait for clock synchronization in seconds
0147  *
0148  * Returns Zero on success, negative of failure.
0149  */
0150 int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
0151 {
0152     int res = -1;
0153 
0154     if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
0155         return res;
0156 
0157     cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]);
0158 
0159     /* Callback to perform SPI4 reset */
0160     INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
0161 
0162     /* NOTE: Calendar setup is not performed during restart */
0163     /*   Refer to cvmx_spi_start_interface() for the full sequence */
0164 
0165     /* Callback to perform clock detection */
0166     INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
0167 
0168     /* Callback to perform SPI4 link training */
0169     INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
0170 
0171     /* Callback to perform calendar sync */
0172     INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
0173           timeout);
0174 
0175     /* Callback to handle interface coming up */
0176     INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
0177 
0178     return res;
0179 }
0180 EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface);
0181 
0182 /*
0183  * Callback to perform SPI4 reset
0184  *
0185  * @interface: The identifier of the packet interface to configure and
0186  *          use as a SPI interface.
0187  * @mode:      The operating mode for the SPI interface. The interface
0188  *          can operate as a full duplex (both Tx and Rx data paths
0189  *          active) or as a halfplex (either the Tx data path is
0190  *          active or the Rx data path is active, but not both).
0191  *
0192  * Returns Zero on success, non-zero error code on failure (will cause
0193  * SPI initialization to abort)
0194  */
0195 int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
0196 {
0197     union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl;
0198     union cvmx_spxx_clk_ctl spxx_clk_ctl;
0199     union cvmx_spxx_bist_stat spxx_bist_stat;
0200     union cvmx_spxx_int_msk spxx_int_msk;
0201     union cvmx_stxx_int_msk stxx_int_msk;
0202     union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
0203     int index;
0204     uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
0205 
0206     /* Disable SPI error events while we run BIST */
0207     spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
0208     cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
0209     stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
0210     cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
0211 
0212     /* Run BIST in the SPI interface */
0213     cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
0214     cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);
0215     spxx_clk_ctl.u64 = 0;
0216     spxx_clk_ctl.s.runbist = 1;
0217     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
0218     __delay(10 * MS);
0219     spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
0220     if (spxx_bist_stat.s.stat0)
0221         cvmx_dprintf
0222             ("ERROR SPI%d: BIST failed on receive datapath FIFO\n",
0223              interface);
0224     if (spxx_bist_stat.s.stat1)
0225         cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n",
0226                  interface);
0227     if (spxx_bist_stat.s.stat2)
0228         cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n",
0229                  interface);
0230 
0231     /* Clear the calendar table after BIST to fix parity errors */
0232     for (index = 0; index < 32; index++) {
0233         union cvmx_srxx_spi4_calx srxx_spi4_calx;
0234         union cvmx_stxx_spi4_calx stxx_spi4_calx;
0235 
0236         srxx_spi4_calx.u64 = 0;
0237         srxx_spi4_calx.s.oddpar = 1;
0238         cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
0239                    srxx_spi4_calx.u64);
0240 
0241         stxx_spi4_calx.u64 = 0;
0242         stxx_spi4_calx.s.oddpar = 1;
0243         cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
0244                    stxx_spi4_calx.u64);
0245     }
0246 
0247     /* Re enable reporting of error interrupts */
0248     cvmx_write_csr(CVMX_SPXX_INT_REG(interface),
0249                cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));
0250     cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
0251     cvmx_write_csr(CVMX_STXX_INT_REG(interface),
0252                cvmx_read_csr(CVMX_STXX_INT_REG(interface)));
0253     cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
0254 
0255     /* Setup the CLKDLY right in the middle */
0256     spxx_clk_ctl.u64 = 0;
0257     spxx_clk_ctl.s.seetrn = 0;
0258     spxx_clk_ctl.s.clkdly = 0x10;
0259     spxx_clk_ctl.s.runbist = 0;
0260     spxx_clk_ctl.s.statdrv = 0;
0261     /* This should always be on the opposite edge as statdrv */
0262     spxx_clk_ctl.s.statrcv = 1;
0263     spxx_clk_ctl.s.sndtrn = 0;
0264     spxx_clk_ctl.s.drptrn = 0;
0265     spxx_clk_ctl.s.rcvtrn = 0;
0266     spxx_clk_ctl.s.srxdlck = 0;
0267     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
0268     __delay(100 * MS);
0269 
0270     /* Reset SRX0 DLL */
0271     spxx_clk_ctl.s.srxdlck = 1;
0272     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
0273 
0274     /* Waiting for Inf0 Spi4 RX DLL to lock */
0275     __delay(100 * MS);
0276 
0277     /* Enable dynamic alignment */
0278     spxx_trn4_ctl.s.trntest = 0;
0279     spxx_trn4_ctl.s.jitter = 1;
0280     spxx_trn4_ctl.s.clr_boot = 1;
0281     spxx_trn4_ctl.s.set_boot = 0;
0282     if (OCTEON_IS_MODEL(OCTEON_CN58XX))
0283         spxx_trn4_ctl.s.maxdist = 3;
0284     else
0285         spxx_trn4_ctl.s.maxdist = 8;
0286     spxx_trn4_ctl.s.macro_en = 1;
0287     spxx_trn4_ctl.s.mux_en = 1;
0288     cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
0289 
0290     spxx_dbg_deskew_ctl.u64 = 0;
0291     cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface),
0292                spxx_dbg_deskew_ctl.u64);
0293 
0294     return 0;
0295 }
0296 
0297 /*
0298  * Callback to setup calendar and miscellaneous settings before clock detection
0299  *
0300  * @interface: The identifier of the packet interface to configure and
0301  *          use as a SPI interface.
0302  * @mode:      The operating mode for the SPI interface. The interface
0303  *          can operate as a full duplex (both Tx and Rx data paths
0304  *          active) or as a halfplex (either the Tx data path is
0305  *          active or the Rx data path is active, but not both).
0306  * @num_ports: Number of ports to configure on SPI
0307  *
0308  * Returns Zero on success, non-zero error code on failure (will cause
0309  * SPI initialization to abort)
0310  */
0311 int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
0312                    int num_ports)
0313 {
0314     int port;
0315     int index;
0316     if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
0317         union cvmx_srxx_com_ctl srxx_com_ctl;
0318         union cvmx_srxx_spi4_stat srxx_spi4_stat;
0319 
0320         /* SRX0 number of Ports */
0321         srxx_com_ctl.u64 = 0;
0322         srxx_com_ctl.s.prts = num_ports - 1;
0323         srxx_com_ctl.s.st_en = 0;
0324         srxx_com_ctl.s.inf_en = 0;
0325         cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
0326 
0327         /* SRX0 Calendar Table. This round robbins through all ports */
0328         port = 0;
0329         index = 0;
0330         while (port < num_ports) {
0331             union cvmx_srxx_spi4_calx srxx_spi4_calx;
0332             srxx_spi4_calx.u64 = 0;
0333             srxx_spi4_calx.s.prt0 = port++;
0334             srxx_spi4_calx.s.prt1 = port++;
0335             srxx_spi4_calx.s.prt2 = port++;
0336             srxx_spi4_calx.s.prt3 = port++;
0337             srxx_spi4_calx.s.oddpar =
0338                 ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);
0339             cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
0340                        srxx_spi4_calx.u64);
0341             index++;
0342         }
0343         srxx_spi4_stat.u64 = 0;
0344         srxx_spi4_stat.s.len = num_ports;
0345         srxx_spi4_stat.s.m = 1;
0346         cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface),
0347                    srxx_spi4_stat.u64);
0348     }
0349 
0350     if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
0351         union cvmx_stxx_arb_ctl stxx_arb_ctl;
0352         union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max;
0353         union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh;
0354         union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl;
0355         union cvmx_stxx_spi4_stat stxx_spi4_stat;
0356         union cvmx_stxx_spi4_dat stxx_spi4_dat;
0357 
0358         /* STX0 Config */
0359         stxx_arb_ctl.u64 = 0;
0360         stxx_arb_ctl.s.igntpa = 0;
0361         stxx_arb_ctl.s.mintrn = 0;
0362         cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);
0363 
0364         gmxx_tx_spi_max.u64 = 0;
0365         gmxx_tx_spi_max.s.max1 = 8;
0366         gmxx_tx_spi_max.s.max2 = 4;
0367         gmxx_tx_spi_max.s.slice = 0;
0368         cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface),
0369                    gmxx_tx_spi_max.u64);
0370 
0371         gmxx_tx_spi_thresh.u64 = 0;
0372         gmxx_tx_spi_thresh.s.thresh = 4;
0373         cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface),
0374                    gmxx_tx_spi_thresh.u64);
0375 
0376         gmxx_tx_spi_ctl.u64 = 0;
0377         gmxx_tx_spi_ctl.s.tpa_clr = 0;
0378         gmxx_tx_spi_ctl.s.cont_pkt = 0;
0379         cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface),
0380                    gmxx_tx_spi_ctl.u64);
0381 
0382         /* STX0 Training Control */
0383         stxx_spi4_dat.u64 = 0;
0384         /*Minimum needed by dynamic alignment */
0385         stxx_spi4_dat.s.alpha = 32;
0386         stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
0387         cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
0388                    stxx_spi4_dat.u64);
0389 
0390         /* STX0 Calendar Table. This round robbins through all ports */
0391         port = 0;
0392         index = 0;
0393         while (port < num_ports) {
0394             union cvmx_stxx_spi4_calx stxx_spi4_calx;
0395             stxx_spi4_calx.u64 = 0;
0396             stxx_spi4_calx.s.prt0 = port++;
0397             stxx_spi4_calx.s.prt1 = port++;
0398             stxx_spi4_calx.s.prt2 = port++;
0399             stxx_spi4_calx.s.prt3 = port++;
0400             stxx_spi4_calx.s.oddpar =
0401                 ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);
0402             cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
0403                        stxx_spi4_calx.u64);
0404             index++;
0405         }
0406         stxx_spi4_stat.u64 = 0;
0407         stxx_spi4_stat.s.len = num_ports;
0408         stxx_spi4_stat.s.m = 1;
0409         cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface),
0410                    stxx_spi4_stat.u64);
0411     }
0412 
0413     return 0;
0414 }
0415 
0416 /*
0417  * Callback to perform clock detection
0418  *
0419  * @interface: The identifier of the packet interface to configure and
0420  *          use as a SPI interface.
0421  * @mode:      The operating mode for the SPI interface. The interface
0422  *          can operate as a full duplex (both Tx and Rx data paths
0423  *          active) or as a halfplex (either the Tx data path is
0424  *          active or the Rx data path is active, but not both).
0425  * @timeout:   Timeout to wait for clock synchronization in seconds
0426  *
0427  * Returns Zero on success, non-zero error code on failure (will cause
0428  * SPI initialization to abort)
0429  */
0430 int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
0431 {
0432     int clock_transitions;
0433     union cvmx_spxx_clk_stat stat;
0434     uint64_t timeout_time;
0435     uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
0436 
0437     /*
0438      * Regardless of operating mode, both Tx and Rx clocks must be
0439      * present for the SPI interface to operate.
0440      */
0441     cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface);
0442     timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
0443     /*
0444      * Require 100 clock transitions in order to avoid any noise
0445      * in the beginning.
0446      */
0447     clock_transitions = 100;
0448     do {
0449         stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
0450         if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
0451             /*
0452              * We've seen a clock transition, so decrement
0453              * the number we still need.
0454              */
0455             clock_transitions--;
0456             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
0457             stat.s.s4clk0 = 0;
0458             stat.s.s4clk1 = 0;
0459         }
0460         if (cvmx_get_cycle() > timeout_time) {
0461             cvmx_dprintf("SPI%d: Timeout\n", interface);
0462             return -1;
0463         }
0464     } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
0465 
0466     cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface);
0467     timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
0468     /*
0469      * Require 100 clock transitions in order to avoid any noise in the
0470      * beginning.
0471      */
0472     clock_transitions = 100;
0473     do {
0474         stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
0475         if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
0476             /*
0477              * We've seen a clock transition, so decrement
0478              * the number we still need
0479              */
0480             clock_transitions--;
0481             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
0482             stat.s.d4clk0 = 0;
0483             stat.s.d4clk1 = 0;
0484         }
0485         if (cvmx_get_cycle() > timeout_time) {
0486             cvmx_dprintf("SPI%d: Timeout\n", interface);
0487             return -1;
0488         }
0489     } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
0490 
0491     return 0;
0492 }
0493 
0494 /*
0495  * Callback to perform link training
0496  *
0497  * @interface: The identifier of the packet interface to configure and
0498  *          use as a SPI interface.
0499  * @mode:      The operating mode for the SPI interface. The interface
0500  *          can operate as a full duplex (both Tx and Rx data paths
0501  *          active) or as a halfplex (either the Tx data path is
0502  *          active or the Rx data path is active, but not both).
0503  * @timeout:   Timeout to wait for link to be trained (in seconds)
0504  *
0505  * Returns Zero on success, non-zero error code on failure (will cause
0506  * SPI initialization to abort)
0507  */
0508 int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
0509 {
0510     union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
0511     union cvmx_spxx_clk_stat stat;
0512     uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
0513     uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
0514     int rx_training_needed;
0515 
0516     /* SRX0 & STX0 Inf0 Links are configured - begin training */
0517     union cvmx_spxx_clk_ctl spxx_clk_ctl;
0518     spxx_clk_ctl.u64 = 0;
0519     spxx_clk_ctl.s.seetrn = 0;
0520     spxx_clk_ctl.s.clkdly = 0x10;
0521     spxx_clk_ctl.s.runbist = 0;
0522     spxx_clk_ctl.s.statdrv = 0;
0523     /* This should always be on the opposite edge as statdrv */
0524     spxx_clk_ctl.s.statrcv = 1;
0525     spxx_clk_ctl.s.sndtrn = 1;
0526     spxx_clk_ctl.s.drptrn = 1;
0527     spxx_clk_ctl.s.rcvtrn = 1;
0528     spxx_clk_ctl.s.srxdlck = 1;
0529     cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
0530     __delay(1000 * MS);
0531 
0532     /* SRX0 clear the boot bit */
0533     spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
0534     spxx_trn4_ctl.s.clr_boot = 1;
0535     cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
0536 
0537     /* Wait for the training sequence to complete */
0538     cvmx_dprintf("SPI%d: Waiting for training\n", interface);
0539     __delay(1000 * MS);
0540     /* Wait a really long time here */
0541     timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
0542     /*
0543      * The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
0544      * We'll be pessimistic and wait for a lot more.
0545      */
0546     rx_training_needed = 500;
0547     do {
0548         stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
0549         if (stat.s.srxtrn && rx_training_needed) {
0550             rx_training_needed--;
0551             cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
0552             stat.s.srxtrn = 0;
0553         }
0554         if (cvmx_get_cycle() > timeout_time) {
0555             cvmx_dprintf("SPI%d: Timeout\n", interface);
0556             return -1;
0557         }
0558     } while (stat.s.srxtrn == 0);
0559 
0560     return 0;
0561 }
0562 
0563 /*
0564  * Callback to perform calendar data synchronization
0565  *
0566  * @interface: The identifier of the packet interface to configure and
0567  *          use as a SPI interface.
0568  * @mode:      The operating mode for the SPI interface. The interface
0569  *          can operate as a full duplex (both Tx and Rx data paths
0570  *          active) or as a halfplex (either the Tx data path is
0571  *          active or the Rx data path is active, but not both).
0572  * @timeout:   Timeout to wait for calendar data in seconds
0573  *
0574  * Returns Zero on success, non-zero error code on failure (will cause
0575  * SPI initialization to abort)
0576  */
0577 int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
0578 {
0579     uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
0580     if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
0581         /* SRX0 interface should be good, send calendar data */
0582         union cvmx_srxx_com_ctl srxx_com_ctl;
0583         cvmx_dprintf
0584             ("SPI%d: Rx is synchronized, start sending calendar data\n",
0585              interface);
0586         srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
0587         srxx_com_ctl.s.inf_en = 1;
0588         srxx_com_ctl.s.st_en = 1;
0589         cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
0590     }
0591 
0592     if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
0593         /* STX0 has achieved sync */
0594         /* The corespondant board should be sending calendar data */
0595         /* Enable the STX0 STAT receiver. */
0596         union cvmx_spxx_clk_stat stat;
0597         uint64_t timeout_time;
0598         union cvmx_stxx_com_ctl stxx_com_ctl;
0599         stxx_com_ctl.u64 = 0;
0600         stxx_com_ctl.s.st_en = 1;
0601         cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
0602 
0603         /* Waiting for calendar sync on STX0 STAT */
0604         cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n",
0605                  interface, interface);
0606         timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
0607         /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */
0608         do {
0609             stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
0610             if (cvmx_get_cycle() > timeout_time) {
0611                 cvmx_dprintf("SPI%d: Timeout\n", interface);
0612                 return -1;
0613             }
0614         } while (stat.s.stxcal == 0);
0615     }
0616 
0617     return 0;
0618 }
0619 
0620 /*
0621  * Callback to handle interface up
0622  *
0623  * @interface: The identifier of the packet interface to configure and
0624  *          use as a SPI interface.
0625  * @mode:      The operating mode for the SPI interface. The interface
0626  *          can operate as a full duplex (both Tx and Rx data paths
0627  *          active) or as a halfplex (either the Tx data path is
0628  *          active or the Rx data path is active, but not both).
0629  *
0630  * Returns Zero on success, non-zero error code on failure (will cause
0631  * SPI initialization to abort)
0632  */
0633 int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode)
0634 {
0635     union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min;
0636     union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max;
0637     union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber;
0638 
0639     if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
0640         union cvmx_srxx_com_ctl srxx_com_ctl;
0641         srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
0642         srxx_com_ctl.s.inf_en = 1;
0643         cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
0644         cvmx_dprintf("SPI%d: Rx is now up\n", interface);
0645     }
0646 
0647     if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
0648         union cvmx_stxx_com_ctl stxx_com_ctl;
0649         stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));
0650         stxx_com_ctl.s.inf_en = 1;
0651         cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
0652         cvmx_dprintf("SPI%d: Tx is now up\n", interface);
0653     }
0654 
0655     gmxx_rxx_frm_min.u64 = 0;
0656     gmxx_rxx_frm_min.s.len = 64;
0657     cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface),
0658                gmxx_rxx_frm_min.u64);
0659     gmxx_rxx_frm_max.u64 = 0;
0660     gmxx_rxx_frm_max.s.len = 64 * 1024 - 4;
0661     cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface),
0662                gmxx_rxx_frm_max.u64);
0663     gmxx_rxx_jabber.u64 = 0;
0664     gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4;
0665     cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64);
0666 
0667     return 0;
0668 }
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