cavium-octeon/executive/cvmx-interrupt-rsl.c

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2008 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /*
0029  * Utility functions to decode Octeon's RSL_INT_BLOCKS
0030  * interrupts into error messages.
0031  */
0032
0033 #include <asm/octeon/octeon.h>
0034
0035 #include <asm/octeon/cvmx-asxx-defs.h>
0036 #include <asm/octeon/cvmx-gmxx-defs.h>
0037
0038 #ifndef PRINT_ERROR
0039 #define PRINT_ERROR(format, ...)
0040 #endif
0041
0042 void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
0043
0044 /**
0045  * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
0046  * CN58XX.
0047  *
0048  * @block:  Interface to enable 0-1
0049  */
0050 void __cvmx_interrupt_asxx_enable(int block)
0051 {
0052     int mask;
0053     union cvmx_asxx_int_en csr;
0054     /*
0055      * CN38XX and CN58XX have two interfaces with 4 ports per
0056      * interface. All other chips have a max of 3 ports on
0057      * interface 0
0058      */
0059     if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
0060         mask = 0xf; /* Set enables for 4 ports */
0061     else
0062         mask = 0x7; /* Set enables for 3 ports */
0063
0064     /* Enable interface interrupts */
0065     csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
0066     csr.s.txpsh = mask;
0067     csr.s.txpop = mask;
0068     csr.s.ovrflw = mask;
0069     cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
0070 }
0071 /**
0072  * Enable GMX error reporting for the supplied interface
0073  *
0074  * @interface: Interface to enable
0075  */
0076 void __cvmx_interrupt_gmxx_enable(int interface)
0077 {
0078     union cvmx_gmxx_inf_mode mode;
0079     union cvmx_gmxx_tx_int_en gmx_tx_int_en;
0080     int num_ports;
0081     int index;
0082
0083     mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
0084
0085     if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
0086         if (mode.s.en) {
0087             switch (mode.cn52xx.mode) {
0088             case 1: /* XAUI */
0089                 num_ports = 1;
0090                 break;
0091             case 2: /* SGMII */
0092             case 3: /* PICMG */
0093                 num_ports = 4;
0094                 break;
0095             default:    /* Disabled */
0096                 num_ports = 0;
0097                 break;
0098             }
0099         } else
0100             num_ports = 0;
0101     } else {
0102         if (mode.s.en) {
0103             if (OCTEON_IS_MODEL(OCTEON_CN38XX)
0104                 || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
0105                 /*
0106                  * SPI on CN38XX and CN58XX report all
0107                  * errors through port 0.  RGMII needs
0108                  * to check all 4 ports
0109                  */
0110                 if (mode.s.type)
0111                     num_ports = 1;
0112                 else
0113                     num_ports = 4;
0114             } else {
0115                 /*
0116                  * CN30XX, CN31XX, and CN50XX have two
0117                  * or three ports. GMII and MII has 2,
0118                  * RGMII has three
0119                  */
0120                 if (mode.s.type)
0121                     num_ports = 2;
0122                 else
0123                     num_ports = 3;
0124             }
0125         } else
0126             num_ports = 0;
0127     }
0128
0129     gmx_tx_int_en.u64 = 0;
0130     if (num_ports) {
0131         if (OCTEON_IS_MODEL(OCTEON_CN38XX)
0132             || OCTEON_IS_MODEL(OCTEON_CN58XX))
0133             gmx_tx_int_en.cn38xx.ncb_nxa = 1;
0134         gmx_tx_int_en.s.pko_nxa = 1;
0135     }
0136     gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
0137     cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
0138     for (index = 0; index < num_ports; index++)
0139         __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
0140 }