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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2009 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 /*
0029  *
0030  * Automatically generated functions useful for enabling
0031  * and decoding RSL_INT_BLOCKS interrupts.
0032  *
0033  */
0034 
0035 #include <asm/octeon/octeon.h>
0036 
0037 #include <asm/octeon/cvmx-gmxx-defs.h>
0038 #include <asm/octeon/cvmx-pcsx-defs.h>
0039 #include <asm/octeon/cvmx-pcsxx-defs.h>
0040 #include <asm/octeon/cvmx-spxx-defs.h>
0041 #include <asm/octeon/cvmx-stxx-defs.h>
0042 
0043 #ifndef PRINT_ERROR
0044 #define PRINT_ERROR(format, ...)
0045 #endif
0046 
0047 
0048 /**
0049  * __cvmx_interrupt_gmxx_rxx_int_en_enable - enable all interrupt bits in cvmx_gmxx_rxx_int_en_t
0050  * @index: interrupt register offset
0051  * @block: interrupt register block_id
0052  */
0053 void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
0054 {
0055     union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
0056     cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
0057                cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
0058     gmx_rx_int_en.u64 = 0;
0059     if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
0060         /* Skipping gmx_rx_int_en.s.reserved_29_63 */
0061         gmx_rx_int_en.s.hg2cc = 1;
0062         gmx_rx_int_en.s.hg2fld = 1;
0063         gmx_rx_int_en.s.undat = 1;
0064         gmx_rx_int_en.s.uneop = 1;
0065         gmx_rx_int_en.s.unsop = 1;
0066         gmx_rx_int_en.s.bad_term = 1;
0067         gmx_rx_int_en.s.bad_seq = 1;
0068         gmx_rx_int_en.s.rem_fault = 1;
0069         gmx_rx_int_en.s.loc_fault = 1;
0070         gmx_rx_int_en.s.pause_drp = 1;
0071         /* Skipping gmx_rx_int_en.s.reserved_16_18 */
0072         /*gmx_rx_int_en.s.ifgerr = 1; */
0073         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0074         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0075         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0076         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0077         gmx_rx_int_en.s.ovrerr = 1;
0078         /* Skipping gmx_rx_int_en.s.reserved_9_9 */
0079         gmx_rx_int_en.s.skperr = 1;
0080         gmx_rx_int_en.s.rcverr = 1;
0081         /* Skipping gmx_rx_int_en.s.reserved_5_6 */
0082         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0083         gmx_rx_int_en.s.jabber = 1;
0084         /* Skipping gmx_rx_int_en.s.reserved_2_2 */
0085         gmx_rx_int_en.s.carext = 1;
0086         /* Skipping gmx_rx_int_en.s.reserved_0_0 */
0087     }
0088     if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
0089         /* Skipping gmx_rx_int_en.s.reserved_19_63 */
0090         /*gmx_rx_int_en.s.phy_dupx = 1; */
0091         /*gmx_rx_int_en.s.phy_spd = 1; */
0092         /*gmx_rx_int_en.s.phy_link = 1; */
0093         /*gmx_rx_int_en.s.ifgerr = 1; */
0094         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0095         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0096         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0097         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0098         gmx_rx_int_en.s.ovrerr = 1;
0099         gmx_rx_int_en.s.niberr = 1;
0100         gmx_rx_int_en.s.skperr = 1;
0101         gmx_rx_int_en.s.rcverr = 1;
0102         /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
0103         gmx_rx_int_en.s.alnerr = 1;
0104         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0105         gmx_rx_int_en.s.jabber = 1;
0106         gmx_rx_int_en.s.maxerr = 1;
0107         gmx_rx_int_en.s.carext = 1;
0108         gmx_rx_int_en.s.minerr = 1;
0109     }
0110     if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
0111         /* Skipping gmx_rx_int_en.s.reserved_20_63 */
0112         gmx_rx_int_en.s.pause_drp = 1;
0113         /*gmx_rx_int_en.s.phy_dupx = 1; */
0114         /*gmx_rx_int_en.s.phy_spd = 1; */
0115         /*gmx_rx_int_en.s.phy_link = 1; */
0116         /*gmx_rx_int_en.s.ifgerr = 1; */
0117         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0118         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0119         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0120         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0121         gmx_rx_int_en.s.ovrerr = 1;
0122         gmx_rx_int_en.s.niberr = 1;
0123         gmx_rx_int_en.s.skperr = 1;
0124         gmx_rx_int_en.s.rcverr = 1;
0125         /* Skipping gmx_rx_int_en.s.reserved_6_6 */
0126         gmx_rx_int_en.s.alnerr = 1;
0127         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0128         gmx_rx_int_en.s.jabber = 1;
0129         /* Skipping gmx_rx_int_en.s.reserved_2_2 */
0130         gmx_rx_int_en.s.carext = 1;
0131         /* Skipping gmx_rx_int_en.s.reserved_0_0 */
0132     }
0133     if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
0134         /* Skipping gmx_rx_int_en.s.reserved_19_63 */
0135         /*gmx_rx_int_en.s.phy_dupx = 1; */
0136         /*gmx_rx_int_en.s.phy_spd = 1; */
0137         /*gmx_rx_int_en.s.phy_link = 1; */
0138         /*gmx_rx_int_en.s.ifgerr = 1; */
0139         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0140         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0141         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0142         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0143         gmx_rx_int_en.s.ovrerr = 1;
0144         gmx_rx_int_en.s.niberr = 1;
0145         gmx_rx_int_en.s.skperr = 1;
0146         gmx_rx_int_en.s.rcverr = 1;
0147         /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
0148         gmx_rx_int_en.s.alnerr = 1;
0149         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0150         gmx_rx_int_en.s.jabber = 1;
0151         gmx_rx_int_en.s.maxerr = 1;
0152         gmx_rx_int_en.s.carext = 1;
0153         gmx_rx_int_en.s.minerr = 1;
0154     }
0155     if (OCTEON_IS_MODEL(OCTEON_CN31XX)) {
0156         /* Skipping gmx_rx_int_en.s.reserved_19_63 */
0157         /*gmx_rx_int_en.s.phy_dupx = 1; */
0158         /*gmx_rx_int_en.s.phy_spd = 1; */
0159         /*gmx_rx_int_en.s.phy_link = 1; */
0160         /*gmx_rx_int_en.s.ifgerr = 1; */
0161         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0162         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0163         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0164         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0165         gmx_rx_int_en.s.ovrerr = 1;
0166         gmx_rx_int_en.s.niberr = 1;
0167         gmx_rx_int_en.s.skperr = 1;
0168         gmx_rx_int_en.s.rcverr = 1;
0169         /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
0170         gmx_rx_int_en.s.alnerr = 1;
0171         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0172         gmx_rx_int_en.s.jabber = 1;
0173         gmx_rx_int_en.s.maxerr = 1;
0174         gmx_rx_int_en.s.carext = 1;
0175         gmx_rx_int_en.s.minerr = 1;
0176     }
0177     if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
0178         /* Skipping gmx_rx_int_en.s.reserved_20_63 */
0179         gmx_rx_int_en.s.pause_drp = 1;
0180         /*gmx_rx_int_en.s.phy_dupx = 1; */
0181         /*gmx_rx_int_en.s.phy_spd = 1; */
0182         /*gmx_rx_int_en.s.phy_link = 1; */
0183         /*gmx_rx_int_en.s.ifgerr = 1; */
0184         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0185         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0186         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0187         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0188         gmx_rx_int_en.s.ovrerr = 1;
0189         gmx_rx_int_en.s.niberr = 1;
0190         gmx_rx_int_en.s.skperr = 1;
0191         gmx_rx_int_en.s.rcverr = 1;
0192         /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
0193         gmx_rx_int_en.s.alnerr = 1;
0194         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0195         gmx_rx_int_en.s.jabber = 1;
0196         gmx_rx_int_en.s.maxerr = 1;
0197         gmx_rx_int_en.s.carext = 1;
0198         gmx_rx_int_en.s.minerr = 1;
0199     }
0200     if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
0201         /* Skipping gmx_rx_int_en.s.reserved_29_63 */
0202         gmx_rx_int_en.s.hg2cc = 1;
0203         gmx_rx_int_en.s.hg2fld = 1;
0204         gmx_rx_int_en.s.undat = 1;
0205         gmx_rx_int_en.s.uneop = 1;
0206         gmx_rx_int_en.s.unsop = 1;
0207         gmx_rx_int_en.s.bad_term = 1;
0208         gmx_rx_int_en.s.bad_seq = 0;
0209         gmx_rx_int_en.s.rem_fault = 1;
0210         gmx_rx_int_en.s.loc_fault = 0;
0211         gmx_rx_int_en.s.pause_drp = 1;
0212         /* Skipping gmx_rx_int_en.s.reserved_16_18 */
0213         /*gmx_rx_int_en.s.ifgerr = 1; */
0214         /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
0215         /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
0216         /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
0217         /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
0218         gmx_rx_int_en.s.ovrerr = 1;
0219         /* Skipping gmx_rx_int_en.s.reserved_9_9 */
0220         gmx_rx_int_en.s.skperr = 1;
0221         gmx_rx_int_en.s.rcverr = 1;
0222         /* Skipping gmx_rx_int_en.s.reserved_5_6 */
0223         /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
0224         gmx_rx_int_en.s.jabber = 1;
0225         /* Skipping gmx_rx_int_en.s.reserved_2_2 */
0226         gmx_rx_int_en.s.carext = 1;
0227         /* Skipping gmx_rx_int_en.s.reserved_0_0 */
0228     }
0229     cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
0230 }
0231 /**
0232  * __cvmx_interrupt_pcsx_intx_en_reg_enable - enable all interrupt bits in cvmx_pcsx_intx_en_reg_t
0233  * @index: interrupt register offset
0234  * @block: interrupt register block_id
0235  */
0236 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
0237 {
0238     union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
0239     cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),
0240                cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
0241     pcs_int_en_reg.u64 = 0;
0242     if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
0243         /* Skipping pcs_int_en_reg.s.reserved_12_63 */
0244         /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
0245         pcs_int_en_reg.s.sync_bad_en = 1;
0246         pcs_int_en_reg.s.an_bad_en = 1;
0247         pcs_int_en_reg.s.rxlock_en = 1;
0248         pcs_int_en_reg.s.rxbad_en = 1;
0249         /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
0250         pcs_int_en_reg.s.txbad_en = 1;
0251         pcs_int_en_reg.s.txfifo_en = 1;
0252         pcs_int_en_reg.s.txfifu_en = 1;
0253         pcs_int_en_reg.s.an_err_en = 1;
0254         /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
0255         /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
0256     }
0257     if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
0258         /* Skipping pcs_int_en_reg.s.reserved_12_63 */
0259         /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
0260         pcs_int_en_reg.s.sync_bad_en = 1;
0261         pcs_int_en_reg.s.an_bad_en = 1;
0262         pcs_int_en_reg.s.rxlock_en = 1;
0263         pcs_int_en_reg.s.rxbad_en = 1;
0264         /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
0265         pcs_int_en_reg.s.txbad_en = 1;
0266         pcs_int_en_reg.s.txfifo_en = 1;
0267         pcs_int_en_reg.s.txfifu_en = 1;
0268         pcs_int_en_reg.s.an_err_en = 1;
0269         /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
0270         /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
0271     }
0272     cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
0273 }
0274 /**
0275  * __cvmx_interrupt_pcsxx_int_en_reg_enable - enable all interrupt bits in cvmx_pcsxx_int_en_reg_t
0276  * @index: interrupt register block_id
0277  */
0278 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
0279 {
0280     union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
0281     cvmx_write_csr(CVMX_PCSXX_INT_REG(index),
0282                cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
0283     pcsx_int_en_reg.u64 = 0;
0284     if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
0285         /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
0286         pcsx_int_en_reg.s.algnlos_en = 1;
0287         pcsx_int_en_reg.s.synlos_en = 1;
0288         pcsx_int_en_reg.s.bitlckls_en = 1;
0289         pcsx_int_en_reg.s.rxsynbad_en = 1;
0290         pcsx_int_en_reg.s.rxbad_en = 1;
0291         pcsx_int_en_reg.s.txflt_en = 1;
0292     }
0293     if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
0294         /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
0295         pcsx_int_en_reg.s.algnlos_en = 1;
0296         pcsx_int_en_reg.s.synlos_en = 1;
0297         pcsx_int_en_reg.s.bitlckls_en = 0;  /* Happens if XAUI module is not installed */
0298         pcsx_int_en_reg.s.rxsynbad_en = 1;
0299         pcsx_int_en_reg.s.rxbad_en = 1;
0300         pcsx_int_en_reg.s.txflt_en = 1;
0301     }
0302     cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
0303 }
0304 
0305 /**
0306  * __cvmx_interrupt_spxx_int_msk_enable - enable all interrupt bits in cvmx_spxx_int_msk_t
0307  * @index: interrupt register block_id
0308  */
0309 void __cvmx_interrupt_spxx_int_msk_enable(int index)
0310 {
0311     union cvmx_spxx_int_msk spx_int_msk;
0312     cvmx_write_csr(CVMX_SPXX_INT_REG(index),
0313                cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
0314     spx_int_msk.u64 = 0;
0315     if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
0316         /* Skipping spx_int_msk.s.reserved_12_63 */
0317         spx_int_msk.s.calerr = 1;
0318         spx_int_msk.s.syncerr = 1;
0319         spx_int_msk.s.diperr = 1;
0320         spx_int_msk.s.tpaovr = 1;
0321         spx_int_msk.s.rsverr = 1;
0322         spx_int_msk.s.drwnng = 1;
0323         spx_int_msk.s.clserr = 1;
0324         spx_int_msk.s.spiovr = 1;
0325         /* Skipping spx_int_msk.s.reserved_2_3 */
0326         spx_int_msk.s.abnorm = 1;
0327         spx_int_msk.s.prtnxa = 1;
0328     }
0329     if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
0330         /* Skipping spx_int_msk.s.reserved_12_63 */
0331         spx_int_msk.s.calerr = 1;
0332         spx_int_msk.s.syncerr = 1;
0333         spx_int_msk.s.diperr = 1;
0334         spx_int_msk.s.tpaovr = 1;
0335         spx_int_msk.s.rsverr = 1;
0336         spx_int_msk.s.drwnng = 1;
0337         spx_int_msk.s.clserr = 1;
0338         spx_int_msk.s.spiovr = 1;
0339         /* Skipping spx_int_msk.s.reserved_2_3 */
0340         spx_int_msk.s.abnorm = 1;
0341         spx_int_msk.s.prtnxa = 1;
0342     }
0343     cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
0344 }
0345 /**
0346  * __cvmx_interrupt_stxx_int_msk_enable - enable all interrupt bits in cvmx_stxx_int_msk_t
0347  * @index: interrupt register block_id
0348  */
0349 void __cvmx_interrupt_stxx_int_msk_enable(int index)
0350 {
0351     union cvmx_stxx_int_msk stx_int_msk;
0352     cvmx_write_csr(CVMX_STXX_INT_REG(index),
0353                cvmx_read_csr(CVMX_STXX_INT_REG(index)));
0354     stx_int_msk.u64 = 0;
0355     if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
0356         /* Skipping stx_int_msk.s.reserved_8_63 */
0357         stx_int_msk.s.frmerr = 1;
0358         stx_int_msk.s.unxfrm = 1;
0359         stx_int_msk.s.nosync = 1;
0360         stx_int_msk.s.diperr = 1;
0361         stx_int_msk.s.datovr = 1;
0362         stx_int_msk.s.ovrbst = 1;
0363         stx_int_msk.s.calpar1 = 1;
0364         stx_int_msk.s.calpar0 = 1;
0365     }
0366     if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
0367         /* Skipping stx_int_msk.s.reserved_8_63 */
0368         stx_int_msk.s.frmerr = 1;
0369         stx_int_msk.s.unxfrm = 1;
0370         stx_int_msk.s.nosync = 1;
0371         stx_int_msk.s.diperr = 1;
0372         stx_int_msk.s.datovr = 1;
0373         stx_int_msk.s.ovrbst = 1;
0374         stx_int_msk.s.calpar1 = 1;
0375         stx_int_msk.s.calpar0 = 1;
0376     }
0377     cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
0378 }
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